/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: suvuctl.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $

// suvuctl.v: 	RSP VU control generation and interlock detection

`timescale 1ns / 10ps

`include "sopcodes.h"

module suvuctl (clk, reset_l, 
	su_inst_a, vu_inst_a, su_inst_b, vu_inst_b, 
	choose_su_inst_b, choose_vu_inst_b, 
	kill_re_non_vu, kill_su_issue, kill_vu_issue,
	vu_reg_hazard_comp, vu_reg_hazard_ls, 
	vu_func, vu_elem, 
	elem_num, vu_comp_k, vu_ld_addr, vu_st_addr, vu_st_xpose_addr, 
	ex_ctc2_vc0, ex_ctc2_vc1, ex_ctc2_vc2, 
	vu_rd_store_type_k, vu_rd_storecfc2_k, 
	rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k, 
	acc_wr_reg, acc_wr_en, 
	xpose);

   input		clk;
   input		reset_l;

   input	[31:0]	su_inst_a;
   input	[31:0]	vu_inst_a;		// RD stage
   input	[31:0]	su_inst_b;
   input	[31:0]	vu_inst_b;		// RD stage
   input		choose_su_inst_b;
   input		choose_vu_inst_b;

   input		kill_re_non_vu;
   input		kill_su_issue;
   input		kill_vu_issue;
   input	[3:0]	elem_num;
   input 		vu_comp_k;

   output		xpose;
						// RD stage to SU
   output		vu_reg_hazard_comp;
   output		vu_reg_hazard_ls;
						// RD stage to VU
   output	[5:0]	vu_func;
   output	[3:0]	vu_elem;
   output	[4:0]	vu_ld_addr;
   output	[4:0]	vu_st_addr;
   output	[4:0]	vu_st_xpose_addr;
   output		vu_rd_store_type_k;
   output		vu_rd_storecfc2_k;
   output		rd_cfvc0_k;
   output		rd_cfvc1_k;
   output		rd_cfvc2_k;
						// EX/ACC stage to VU
   output		ex_ctc2_vc0;
   output		ex_ctc2_vc1;
   output		ex_ctc2_vc2;
						// DF stage to VU
   output	[4:0]   acc_wr_reg;    	
   output		acc_wr_en;

   wire 	[31:0] 	su_inst;
   wire 	[31:0] 	vu_inst;
   wire         [5:0]	opc;
   wire         [5:0]	func;
   wire         [4:0]	rs;
   wire         [4:0]	rt;
   wire         [4:0]	rd;

   wire			rd_mfc2;
   wire			vu_rd_store_type;
   wire			vu_rd_storecfc2;
   wire		[4:0]	rd_st_src;

   // VU Pipe Signals:

   wire			vu_comp;
   wire		[4:0]	vd;
   wire		[4:0]	vd_a;
   wire		[4:0]	vd_b;
   wire		[4:0]	vu_ld_reg;
   wire		[4:0]	vu_st_reg;
   wire		[4:0]	vu_mf_reg;
   wire			mul_ld_en;
   wire			acc_ld_en;
   wire			wbv_ld_en;
   wire			mul_ld_xpose;
   wire			acc_ld_xpose;
   wire		[4:0]	mul_ld_reg;
   wire		[4:0]	acc_ld_reg;
   wire		[4:0]	wbv_ld_reg;
   wire			mul_wr_en;
   wire			wbv_wr_en;  	
   wire		[4:0]	mul_wr_reg;
   wire		[4:0]	acc_ld_dest;
   wire		[2:0]	df_elem_num;

   wire			ctc2_vc0;
   wire			ctc2_vc1;
   wire			ctc2_vc2;
   wire			ctc2_vc0_k;
   wire			ctc2_vc1_k;
   wire			ctc2_vc2_k;
   wire			rd_cfvc0;
   wire			rd_cfvc1;
   wire			rd_cfvc2;

   wire			ld_xpose;
   wire			st_xpose_a;
   wire			st_xpose_b;

   wire			use_vs;
   wire			use_vt;
   wire			use_mf_reg;
   wire			use_st_reg;

   wire			vu_rd_ld_en;
   wire			vu_rd_ld_en_k;

   wire		[31:0]	mul_dest_bit_mask_n; 
   wire		[31:0]	acc_dest_bit_mask_n;
   wire		[31:0]	dest_bit_mask_n;
   wire			mul_ld_en_n; 
   wire		[4:0]	mul_ld_reg_n;
   wire			mul_ld_xpose_n;
   wire			mul_wr_en_n;
   wire		[4:0]	mul_wr_reg_n; 
   wire			ex_ctc2_vc0_n;
   wire			ex_ctc2_vc1_n;
   wire			ex_ctc2_vc2_n;
   wire			acc_ld_en_n;
   wire		[4:0]	acc_ld_reg_n;
   wire			acc_ld_xpose_n;
   wire			acc_wr_en_n;
   wire		[4:0]	acc_wr_reg_n;
   wire		[2:0]	df_elem_num_n;

   //
   // RD stage signals: instruction decode, bypasses 
   //

   assign opc = su_inst[31:26];
   assign func = su_inst[5:0];
   assign rs = su_inst[25:21];
   assign rt = su_inst[20:16];
   assign rd = su_inst[15:11];

   assign rd_mfc2 = (opc[5:4]==2'b01) && (opc[1]==1'b1) && 
        (rs[4]==0) && (rs[2:1]==2'b00);

// VU Pipe Control, Take 2
   
   wire		[5:0]	opc_a;
   wire		[5:0]	vu_func_a;
   wire			vu_comp_a;
   wire		[4:0]	rs_a;
   wire		[4:0]	rt_a;
   wire		[4:0]	rd_a;
   wire		[4:0]	vs_a;
   wire		[4:0]	vt_a;
   wire			use_vs_a;
   wire			use_vt_a;
   wire			use_mf_a_reg;
   wire			use_st_a_reg;
   wire 	[31:0]	xpose_bit_mask_a;
   wire 	[31:0]	vs_a_decode_l;
   wire		[31:0]	vt_a_decode_l;
   wire		[31:0]	rt_a_decode_l;
   wire		[31:0]	rd_a_decode_l;
   wire		[31:0]	vs_bit_mask_a;
   wire		[31:0]	vt_bit_mask_a;
   wire		[31:0]	mf_bit_mask_a;
   wire		[31:0]	st_bit_mask_a;

   wire		[5:0]	opc_b;
   wire		[5:0]	vu_func_b;
   wire			vu_comp_b;
   wire		[4:0]	rs_b;
   wire		[4:0]	rt_b;
   wire		[4:0]	rd_b;
   wire		[4:0]	vs_b;
   wire		[4:0]	vt_b;
   wire			use_vs_b;
   wire			use_vt_b;
   wire			use_mf_b_reg;
   wire			use_st_b_reg;
   wire 	[31:0]	xpose_bit_mask_b;
   wire 	[31:0]	vs_b_decode_l;
   wire		[31:0]	vt_b_decode_l;
   wire		[31:0]	rt_b_decode_l;
   wire		[31:0]	rd_b_decode_l;
   wire		[31:0]	vs_bit_mask_b;
   wire		[31:0]	vt_bit_mask_b;
   wire		[31:0]	mf_bit_mask_b;
   wire		[31:0]	st_bit_mask_b;


   wire 	[31:0]	vs_decode_l;
   wire		[31:0]	vt_decode_l;
   wire		[31:0]	vd_decode_l;
   wire		[31:0]	vd_a_decode_l;
   wire		[31:0]	vd_b_decode_l;
   wire		[31:0]	rt_decode_l;
   wire		[31:0]	rd_decode_l;
   wire		[31:0]	vs_bit_mask;
   wire		[31:0]	vt_bit_mask;
   wire		[31:0]	mf_bit_mask;
   wire		[31:0]	st_bit_mask;
   wire		[31:0]	vd_bit_mask;
   wire		[31:0]	vd_a_bit_mask;
   wire		[31:0]	vd_b_bit_mask;
   wire		[31:0]	ld_bit_mask;
   wire		[31:0]	mt_bit_mask;
   wire		[31:0]	rd_dest_bit_mask_k;
   wire		[31:0]	mul_dest_bit_mask;
   wire		[31:0]	acc_dest_bit_mask;

   assign opc_a = su_inst_a[31:26];
   assign rs_a = su_inst_a[25:21];
   assign rt_a = su_inst_a[20:16];
   assign rd_a = su_inst_a[15:11];

   assign vu_comp_a = (vu_inst_a[31:25] == 7'b0100101) && 	// nop
	!((vu_func_a == 6'b110111) || (vu_func_a == 6'b111111));	
   assign vu_func_a = vu_inst_a[5:0];


   assign use_vs_a = 
	 vu_comp_a && !((vu_func_a[5:4] == 2'b11) ||    // !div-class
 		      (vu_func_a[5:0] == 6'b001011) ||  // !macq
 		      (vu_func_a[5:0] == 6'b011100) ||  // !vsum
		      (vu_func_a[5:0] == 6'b000010) ||  // !rnd
		      (vu_func_a[5:0] == 6'b001010) ||  // !rnd
		      (vu_func_a[5:2] == 4'b0111));     // !sar
   assign use_vt_a = 
	 vu_comp_a && !((vu_func_a[5:0] == 6'b001011) || // !macq
		      (vu_func_a[5:0] == 6'b011100) ||  // !vsum
		      (vu_func_a[5:2] == 4'b1111) ||    // !extract
		      (vu_func_a[5:2] == 4'b0111));     // !sar
   assign use_mf_a_reg = (opc_a=='h12) && (rs_a=='h00); // `COP2 && `MFC;  
   assign use_st_a_reg = (opc_a=='h3a);			// SWC2


   assign xpose_bit_mask_a[7:0] = 
	{8{(su_inst_a[14:11]==4'b1011)}} & {8{rt_a[4:3]==2'b00}};
   assign xpose_bit_mask_a[15:8]  = 
	{8{(su_inst_a[14:11]==4'b1011)}} & {8{rt_a[4:3]==2'b01}};
   assign xpose_bit_mask_a[23:16] = 
	{8{(su_inst_a[14:11]==4'b1011)}} & {8{rt_a[4:3]==2'b10} };
   assign xpose_bit_mask_a[31:24] = 
	{8{(su_inst_a[14:11]==4'b1011)}} & {8{rt_a[4:3]==2'b11}};

   sp_5_32_decode vs_a_dec (vs_a_decode_l, vs_a);
   sp_5_32_decode vt_a_dec (vt_a_decode_l, vt_a);
   sp_5_32_decode rt_a_dec (rt_a_decode_l, rt_a);
   sp_5_32_decode rd_a_dec (rd_a_decode_l, rd_a);

   assign vs_bit_mask_a = {32{use_vs_a}} & ~vs_a_decode_l;
   assign vt_bit_mask_a = {32{use_vt_a}} & ~vt_a_decode_l;
   assign mf_bit_mask_a = {32{use_mf_a_reg}} & ~rd_a_decode_l;
   assign st_bit_mask_a = {32{use_st_a_reg}} & (xpose_bit_mask_a | ~rt_a_decode_l);

   assign opc_b = su_inst_b[31:26];
   assign rs_b = su_inst_b[25:21];
   assign rt_b = su_inst_b[20:16];
   assign rd_b = su_inst_b[15:11];
   assign vu_comp_b = (vu_inst_b[31:25] == 7'b0100101) && 	// nop
	!((vu_func_b == 6'b110111) || (vu_func_b == 6'b111111));	
   assign vu_func_b = vu_inst_b[5:0];


   assign use_vs_b = 
	 vu_comp_b && !((vu_func_b[5:4] == 2'b11) ||    // !div-class
 		      (vu_func_b[5:0] == 6'b001011) ||  // !macq
 		      (vu_func_b[5:0] == 6'b011100) ||  // !vsum
		      (vu_func_b[5:0] == 6'b000010) ||  // !rnd
		      (vu_func_b[5:0] == 6'b001010) ||  // !rnd
		      (vu_func_b[5:2] == 4'b0111));     // !sar
   assign use_vt_b = 
	 vu_comp_b && !((vu_func_b[5:0] == 6'b001011) || // !macq
		      (vu_func_b[5:0] == 6'b011100) ||  // !vsum
		      (vu_func_b[5:2] == 4'b1111) ||    // !extract
		      (vu_func_b[5:2] == 4'b0111));     // !sar
   assign use_mf_b_reg = (opc_b=='h12) && (rs_b=='h00); // `COP2 && `MFC;  
   assign use_st_b_reg = (opc_b=='h3a);			// SWC2


   assign xpose_bit_mask_b[7:0] = 
	{8{(su_inst_b[14:11]==4'b1011)}} & {8{rt_b[4:3]==2'b00}};
   assign xpose_bit_mask_b[15:8]  = 
	{8{(su_inst_b[14:11]==4'b1011)}} & {8{rt_b[4:3]==2'b01}};
   assign xpose_bit_mask_b[23:16] = 
	{8{(su_inst_b[14:11]==4'b1011)}} & {8{rt_b[4:3]==2'b10} };
   assign xpose_bit_mask_b[31:24] = 
	{8{(su_inst_b[14:11]==4'b1011)}} & {8{rt_b[4:3]==2'b11}};

   sp_5_32_decode vs_b_dec (vs_b_decode_l, vs_b);
   sp_5_32_decode vt_b_dec (vt_b_decode_l, vt_b);
   sp_5_32_decode rt_b_dec (rt_b_decode_l, rt_b);
   sp_5_32_decode rd_b_dec (rd_b_decode_l, rd_b);

   assign vs_bit_mask_b = {32{use_vs_b}} & ~vs_b_decode_l;
   assign vt_bit_mask_b = {32{use_vt_b}} & ~vt_b_decode_l;
   assign mf_bit_mask_b = {32{use_mf_b_reg}} & ~rd_b_decode_l;
   assign st_bit_mask_b = {32{use_st_b_reg}} & (xpose_bit_mask_b | ~rt_b_decode_l);

   assign su_inst = choose_su_inst_b ? su_inst_b : su_inst_a;
   assign vu_inst = choose_vu_inst_b ? vu_inst_b : vu_inst_a;
   assign vd_a = vu_inst_a[10:6];
   assign vd_b = vu_inst_b[10:6];
   assign vd = choose_vu_inst_b ? vu_inst_b[10:6] : vu_inst_a[10:6];

   sp_5_32_decode vd_a_dec (vd_a_decode_l, vd_a);
   sp_5_32_decode vd_b_dec (vd_b_decode_l, vd_b);
   assign vd_bit_mask = choose_vu_inst_b ?
   	({32{vu_comp_b}} & ~vd_b_decode_l) :
	({32{vu_comp_a}} & ~vd_a_decode_l);
   assign ld_bit_mask = choose_su_inst_b ? 		// LWC2
	({32{opc_b=='h32}} & (xpose_bit_mask_b | ~rt_b_decode_l)) : 
	({32{opc_a=='h32}} & (xpose_bit_mask_a | ~rt_a_decode_l));
   assign mt_bit_mask = choose_su_inst_b ? 		// MTC
	({32{(opc_b=='h12 && rs_b=='h04)}} & ~rd_b_decode_l) : 
	({32{(opc_a=='h12 && rs_a=='h04)}} & ~rd_a_decode_l);

   assign rd_dest_bit_mask_k = 
	({32{!(kill_vu_issue || kill_re_non_vu || vu_reg_hazard_comp || (vu_reg_hazard_ls && !kill_su_issue))}} & vd_bit_mask) | 
	({32{!(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue))}} & (ld_bit_mask | mt_bit_mask));
   spasdff_32_0 su_re_dest_mask_ff (mul_dest_bit_mask, mul_dest_bit_mask_n, rd_dest_bit_mask_k, clk, reset_l);
   spasdff_32_0 su_ed_dest_mask_ff (acc_dest_bit_mask, acc_dest_bit_mask_n, mul_dest_bit_mask, clk, reset_l);


   wire [31:0] early_dest_bit_mask;
   wire [31:0] dest_bit_mask;

   assign early_dest_bit_mask = 
	rd_dest_bit_mask_k | mul_dest_bit_mask | acc_dest_bit_mask;
   spasdff_32_0 su_dest_mask_ff (dest_bit_mask, dest_bit_mask_n, early_dest_bit_mask, clk,   reset_l); 

   assign vs_bit_mask = choose_vu_inst_b ? vs_bit_mask_b : vs_bit_mask_a;
   assign vt_bit_mask = choose_vu_inst_b ? vt_bit_mask_b : vt_bit_mask_a;
   assign mf_bit_mask = choose_su_inst_b ? mf_bit_mask_b : mf_bit_mask_a;
   assign st_bit_mask = choose_su_inst_b ? st_bit_mask_b : st_bit_mask_a;

   assign vu_reg_hazard_ls = 
	(dest_bit_mask & (mf_bit_mask | st_bit_mask)) != 0;

   assign vu_reg_hazard_comp = 
	(dest_bit_mask & (vs_bit_mask | vt_bit_mask)) != 0;

   assign vu_func = choose_vu_inst_b ? vu_func_b : vu_func_a;

   assign ld_xpose = `LWC2 && (su_inst[14:11]==4'b1011);
   assign st_xpose_a =  (su_inst_a[31:26]==6'b111010) && 
			(su_inst_a[14:11]==4'b1011);
   assign st_xpose_b =  (su_inst_b[31:26]==6'b111010) && 
			(su_inst_b[14:11]==4'b1011);

   assign rd_cfvc0 = `COP2 && `CFC && (rd[1:0]==2'b00);
   assign ctc2_vc0 = `COP2 && `CTC && (rd[1:0]==2'b00);
   assign rd_cfvc1 = `COP2 && `CFC && (rd[1:0]==2'b01);
   assign ctc2_vc1 = `COP2 && `CTC && (rd[1:0]==2'b01);
   assign rd_cfvc2 = `COP2 && `CFC && (rd[1:0]==2'b10);
   assign ctc2_vc2 = `COP2 && `CTC && (rd[1:0]==2'b10);

   // *** Some of the followign should be generate from their _a and _b 
   // versions.

   assign vu_comp = choose_vu_inst_b ? vu_comp_b : vu_comp_a;

   assign vu_rd_ld_en = `LWC2 || (`COP2 && `MTC);
   assign vu_ld_reg = `LWC2 ? rt : rd;
   assign vu_st_reg = rt;
   assign vu_mf_reg = rd;


   assign use_vs = 
	 vu_comp && !((vu_func[5:4] == 2'b11) ||      // !div-class
 		      (vu_func[5:0] == 6'b001011) ||  // !macq
 		      (vu_func[5:0] == 6'b011100) ||  // !vsum
		      (vu_func[5:0] == 6'b000010) ||  // !rnd
		      (vu_func[5:0] == 6'b001010) ||  // !rnd
		      (vu_func[5:2] == 4'b0111));     // !sar
   assign use_vt = 
	 vu_comp && !((vu_func[5:0] == 6'b001011) ||  // !macq
		      (vu_func[5:0] == 6'b011100) ||  // !vsum
		      (vu_func[5:2] == 4'b1111) ||    // !extract
		      (vu_func[5:2] == 4'b0111));     // !sar

   assign use_mf_reg = `COP2 && `MFC;  
   assign use_st_reg = `SWC2;

   // VU control register hazards:
   // There aren't any involving outstanding writes, because the control 
   // registers are both read and written (by both computation instructions
   // and CTC2/CFC2) in the EX stage.  The only hazards involve dual issuing
   // instructions both of which want to access the same control register.
   // This is handled in the issue logic.

   // Kill: optionally kill EX stage signals

   assign vu_rd_ld_en_k = vu_rd_ld_en && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign ctc2_vc0_k = ctc2_vc0 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign ctc2_vc1_k = ctc2_vc1 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign ctc2_vc2_k = ctc2_vc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));

   spasdff_1_0 su_re_vulden_ff(mul_ld_en,mul_ld_en_n, vu_rd_ld_en_k, clk, reset_l);
   spasdff_5_0 su_re_vu_ld_reg_ff(mul_ld_reg,mul_ld_reg_n, vu_ld_reg, clk, reset_l);
   spasdff_1_0 su_re_vu_xp_ff(mul_ld_xpose,mul_ld_xpose_n, ld_xpose, clk, reset_l);
   spasdff_1_0 su_re_vuwren_ff(mul_wr_en,mul_wr_en_n,vu_comp_k,clk,reset_l);
   spasdff_5_0 su_re_vu_wr_reg_ff(mul_wr_reg,mul_wr_reg_n, vd, clk, reset_l);
   spasdff_1_0 su_re_vu_ct0_ff(ex_ctc2_vc0,ex_ctc2_vc0_n, ctc2_vc0_k, clk, reset_l);
   spasdff_1_0 su_re_vu_ct1_ff(ex_ctc2_vc1,ex_ctc2_vc1_n, ctc2_vc1_k, clk, reset_l);
   spasdff_1_0 su_re_vu_ct2_ff(ex_ctc2_vc2,ex_ctc2_vc2_n, ctc2_vc2_k, clk, reset_l);

   spasdff_1_0 su_ed_vu_ld_en_ff(acc_ld_en,acc_ld_en_n, mul_ld_en, clk, reset_l);
   spasdff_5_0 su_ed_vu_ld_reg_ff(acc_ld_reg,acc_ld_reg_n, mul_ld_reg, clk, reset_l);
   spasdff_1_0 su_ed_vu_xp_en_ff(acc_ld_xpose,acc_ld_xpose_n, mul_ld_xpose, clk, reset_l);
   spasdff_1_0 su_ed_vu_wr_en_ff(acc_wr_en,acc_wr_en_n, mul_wr_en, clk, reset_l);
   spasdff_5_0 su_ed_vu_wr_reg_ff(acc_wr_reg,acc_wr_reg_n, mul_wr_reg, clk, reset_l);
   spasdff_3_0 su_ed_elem_ff(df_elem_num,df_elem_num_n, elem_num[3:1], clk,reset_l);

/* ********************************************************************** */

// VU Control Generation:

   assign vu_rd_store_type = `SWC2 || (`COP2 && `MFC); 
   assign vu_rd_storecfc2 = `SWC2 || (`COP2 && (`MFC || `CFC)); 
   assign vu_elem = vu_inst[24:21];	// *** used for vu_comp insts?

   function [4:0] rd_st_src_mux;
       input [4:0] rd_st_src_sel;
       input [4:0] in_a, in_b, in_c, in_d;
       begin
           case (1'b1)          // synopsys parallel_case full_case
               rd_st_src_sel[0] : rd_st_src_mux = in_a;
               rd_st_src_sel[1] : rd_st_src_mux = in_b;
               rd_st_src_sel[2] : rd_st_src_mux = in_c;
               default		: rd_st_src_mux = in_d;
           endcase
       end
   endfunction

   wire [2:0] rd_st_src_sel;
   assign rd_st_src_sel[0] = rd_mfc2;
   assign rd_st_src_sel[1] = !rd_mfc2 && choose_su_inst_b && st_xpose_b;
   assign rd_st_src_sel[2] = !rd_mfc2 && !choose_su_inst_b && st_xpose_a;

   assign rd_st_src = rd_st_src_mux(rd_st_src_sel, 
	su_inst[15:11], {su_inst_b[20:19], su_inst_b[10:8]}, 
	{su_inst_a[20:19], su_inst_a[10:8]}, su_inst[20:16]);

   assign xpose = (acc_ld_en && acc_ld_xpose) || 
		  (!acc_ld_en && choose_su_inst_b && st_xpose_b) ||
		  (!acc_ld_en && !choose_su_inst_b && st_xpose_a);

   assign rd_cfvc0_k = rd_cfvc0 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign rd_cfvc1_k = rd_cfvc1 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign rd_cfvc2_k = rd_cfvc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign vu_rd_store_type_k = vu_rd_store_type && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));
   assign vu_rd_storecfc2_k = vu_rd_storecfc2 && !(kill_su_issue || kill_re_non_vu || vu_reg_hazard_ls || (vu_reg_hazard_comp && !kill_vu_issue));


   wire [4:0] vu_st_addr_a;
   wire [4:0] vu_st_xpose_addr_a;
   wire [4:0] vu_st_addr_b;
   wire [4:0] vu_st_xpose_addr_b;
   assign vu_ld_addr = 
	acc_ld_xpose ? {acc_ld_reg[4:3], df_elem_num} : acc_ld_reg;

   function [4:0] vu_st_addr_mux;
       input [4:0] vu_st_addr_sel;
       input [4:0] in_a, in_b, in_c, in_d;
       begin
           case (1'b1)          // synopsys parallel_case full_case
               vu_st_addr_sel[0] : vu_st_addr_mux = in_a;
               vu_st_addr_sel[1] : vu_st_addr_mux = in_b;
               vu_st_addr_sel[2] : vu_st_addr_mux = in_c;
               vu_st_addr_sel[3] : vu_st_addr_mux = in_d;
           endcase
       end
   endfunction

   wire [3:0] vu_st_addr_sel;
   assign vu_st_addr_sel[0] = !choose_su_inst_b && su_inst_a[29];
   assign vu_st_addr_sel[1] = !choose_su_inst_b && !su_inst_a[29];
   assign vu_st_addr_sel[2] = choose_su_inst_b && su_inst_b[29];
   assign vu_st_addr_sel[3] = choose_su_inst_b && !su_inst_b[29];

   assign vu_st_addr = vu_st_addr_mux(vu_st_addr_sel, 
	su_inst_a[20:16], su_inst_a[15:11],		// mfc2 or not
	su_inst_b[20:16], su_inst_b[15:11]);

/*
   assign vu_st_addr_a = 				// mfc2 or not
	su_inst_a[29] ? su_inst_a[20:16] : su_inst_a[15:11];
   assign vu_st_addr_b = 				// mfc2 or not
	su_inst_b[29] ? su_inst_b[20:16] : su_inst_b[15:11];
   assign vu_st_addr = 
	choose_su_inst_b ? vu_st_addr_b : vu_st_addr_a;
*/

   assign vu_st_xpose_addr_a = {su_inst_a[20:19], su_inst_a[10:8]};
   assign vu_st_xpose_addr_b = {su_inst_b[20:19], su_inst_b[10:8]};
   assign vu_st_xpose_addr = 
	choose_su_inst_b ? vu_st_xpose_addr_b : vu_st_xpose_addr_a;
   assign vs_a = vu_inst_a[15:11];
   assign vs_b = vu_inst_b[15:11];
   assign vt_a = vu_inst_a[20:16];
   assign vt_b = vu_inst_b[20:16];

endmodule