create_clock clock -period 17.6 -waveform {0.0 8.8}


set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
set_input_delay 2.5 -clock clk {single_step};
set_input_delay 2.5 -clock clk {pc_in_wr_en};
set_input_delay 2.5 -clock clk {pc_data_in};
set_input_delay 11.0 -clock clk {pc_sel};
set_input_delay 8.0 -clock clk {halting};
set_input_delay 8.5 -clock clk {br_addr};
set_input_delay 1.5 -clock clk {rd_inst};

set_input_delay 12.0 -clock clk {set_broke};
set_input_delay 14.5 -clock clk {wr_br_addr};
set_input_delay 2.0 -clock clk {imem_dma_pif};
set_input_delay 5.0 -clock clk {taken};
set_input_delay 1.5 -clock clk {old_taken};
set_input_delay 9.5 -clock clk {adv_ir};
set_input_delay 10.0 -clock clk {kill_re};
set_input_delay 12.0 -clock clk {should_have_stalled};

set_input_delay 2.0 -clock clk {old_delay_pending};
set_input_delay 10.0 -clock clk {clear_target_pending};	/* really 11.0 */
set_input_delay 2.0 -clock clk {old_target_pending};

set_driving_cell -cell ni01d5 -pin z {rd_inst};

set_output_delay -max 13.27 -clock clk {su_inst_a};
set_output_delay -max 13.27 -clock clk {vu_inst_a};
set_output_delay -max 13.0 -clock clk {su_inst_b};
set_output_delay -max 13.0 -clock clk {vu_inst_b};
set_output_delay -max 11.7 -clock clk {choose_su_inst_b}; /* *** s.b. 12.0 */
set_output_delay -max 11.7 -clock clk {choose_vu_inst_b}; /* *** s.b. 12.0 */
set_output_delay -max 7.6 -clock clk {link_pc_delay_pc}; 
set_output_delay -max 14.4 -clock clk {pc};
set_output_delay -max 3.25 -clock clk {pc_wr_en};
set_output_delay -max 15.6 -clock clk {rd_bubble};
set_output_delay -max 15.6 -clock clk {br_target};
set_output_delay -max 13.6 -clock clk {delay_slot};
set_output_delay -max 6.1 -clock clk {imem_stall};
set_output_delay -max 13.5 -clock clk {start_ext_halt};
set_output_delay -max 7.04 -clock clk {kill_su_issue};	/* *** s.b. 7.0 */
set_output_delay -max 7.04 -clock clk {kill_vu_issue};	/* *** s.b. 7.0 */
set_output_delay -max 7.6 -clock clk {vu_comp};
set_output_delay -max 9.45 -clock clk {vs};
set_output_delay -max 3.6 -clock clk {vs_eq_one};
set_output_delay -max 16.1 -clock clk {rd_pre_vt};
set_output_delay -max 13.3 -clock clk {vt_sel};

set_load .7 {pc};
set_load 1.7 {vs}; 
set_load 1.7 {vs_eq_one};

set_max_transition 1.45 {vs}
set_max_transition 1.45 {vs_eq_one}