set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
set_input_delay 2.5 -clock clk {single_step};
set_input_delay 2.5 -clock clk {pc_in_wr_en};
set_input_delay 2.5 -clock clk {pc_data_in[*]};
set_input_delay 2.5 -clock clk {dma_dm_to_rd};
set_input_delay 2.5 -clock clk {dma_rd_to_dm};
set_input_delay 2.5 -clock clk {dma_imem_select};
set_input_delay 1.5 -clock clk {rd_inst};

set_driving_cell -cell ni01d5 -pin z {rd_inst};

set_output_delay -max 1.5 -clock clk {rd_base};
set_output_delay -max 4.0 -clock clk {rd_offset};
set_output_delay -max 8.0 -clock clk {rd_elem_num};

set_output_delay -max 10.0 -clock clk {chip_sel}; 
set_output_delay -max 14.0 -clock clk {su_ex_store};
set_output_delay -max 14.0 -clock clk {su_ex_load};
set_output_delay -max 14.0 -clock clk {vu_ex_store};
set_output_delay -max 14.0 -clock clk {vu_ex_load};
set_output_delay -max 14.0 -clock clk {ex_mfc2};
set_output_delay -max 14.0 -clock clk {ex_mtc2};
set_output_delay -max 14.0 -clock clk {ex_cfc2};
set_output_delay -max 14.0 -clock clk {ex_mfc0};
set_output_delay -max 14.0 -clock clk {ex_su_byte_ls};
set_output_delay -max 14.0 -clock clk {ex_su_half_ls};
set_output_delay -max 14.0 -clock clk {ex_su_uns_ls};
set_output_delay -max 14.0 -clock clk {df_ls_drive_ls_in_wb};
set_output_delay -max 14.0 -clock clk {df_pass_thru}; 

set_output_delay -max 11.0 -clock clk {imem_chip_sel_l};
set_output_delay -max 11.0 -clock clk {imem_dma_cycle}; 
set_output_delay -max 12.8 -clock clk {pc};

set_output_delay 7.5 -clock clk {branch_or_addr};

set_output_delay -max 14.0 -clock clk {elem_num};
set_output_delay -max 4.0 -clock clk {set_broke};

set_input_delay 14.0 -clock clk {ls_data};
set_output_delay -max 12.0 -clock clk {ls_data};
 
set_output_delay -max 5.0 -clock clk {vu_comp_k};
set_output_delay -max 9.0 -clock clk {vu_func};
set_output_delay -max 8.0 -clock clk {ex_ctc2_vc0};
set_output_delay -max 8.0 -clock clk {ex_ctc2_vc1};
set_output_delay -max 8.0 -clock clk {ex_ctc2_vc2};
set_output_delay -max 3.0 -clock clk {vu_rd_store_type_k};
set_output_delay -max 3.0 -clock clk {vu_rd_storecfc2_k};
set_output_delay -max 3.0 -clock clk {vs_eq_one};
set_output_delay -max 9.0 -clock clk {vu_elem};
set_output_delay -max 6.0 -clock clk {vu_ld_addr};
set_output_delay -max 9.0 -clock clk {vu_st_addr};
set_output_delay -max 9.0 -clock clk {vu_st_xpose_addr};
set_output_delay -max 10.0 -clock clk {vs}; 
set_output_delay -max 11.0 -clock clk {vt}; 
set_output_delay -max 10.0 -clock clk {acc_wr_reg}; 
set_output_delay -max 10.0 -clock clk {acc_wr_en};
set_output_delay -max 9.5 -clock clk {xpose};
set_output_delay -max 3.0 -clock clk {rd_cfvc0_k};
set_output_delay -max 3.0 -clock clk {rd_cfvc1_k};
set_output_delay -max 3.0 -clock clk {rd_cfvc2_k};
 
set_output_delay -max 13.0 -clock clk {cp0_address};
set_output_delay -max 13.0 -clock clk {cp0_write}; 
set_output_delay -max 13.0 -clock clk {cp0_enable};