create_clock clock -period 18.5 -waveform {0.0 9.25}

set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
set_input_delay 2.5 -clock clk {single_step};
set_input_delay 2.5 -clock clk {pc_in_wr_en};
set_input_delay 2.5 -clock clk {pc_data_in};
set_input_delay 2.5 -clock clk {dma_dm_to_rd};
set_input_delay 2.5 -clock clk {dma_rd_to_dm};
set_input_delay 2.5 -clock clk {dma_imem_select};
set_input_delay 8.5 -clock clk {br_addr};
set_input_delay 1.5 -clock clk {rd_inst};

set_input_delay 12.5 -clock clk {sushvamt};
set_input_delay 8.5 -clock clk {sualu_cout_l};
set_input_delay 8.5 -clock clk {sualu_ovr};
set_input_delay 9.5 -clock clk {sualumsb};
set_input_delay 1.5 -clock clk {suexasign};
set_input_delay 1.5 -clock clk {suexbsign};
set_input_delay 3.5 -clock clk {suonesdet_z};

set_driving_cell -cell ni01d5 -pin z {rd_inst};

set_output_delay -max 4.0 -clock clk {rd_base};
set_output_delay -max 2.15 -clock clk {rd_cfvc0_k};
set_output_delay -max 2.15 -clock clk {rd_cfvc1_k};
set_output_delay -max 2.15 -clock clk {rd_cfvc2_k};
set_output_delay -max 0.4 -clock clk {vu_rd_ld_dec_k};
set_output_delay -max 0.4 -clock clk {vu_rd_st_dec_k};
set_output_delay -max 1.85 -clock clk {set_broke};
set_output_delay -max 4.5 -clock clk {vs_eq_one};
set_output_delay -max 2.4 -clock clk {vu_rd_store_type_k};
set_output_delay -max 2.4 -clock clk {vu_rd_storecfc2_k};
set_output_delay -max 4.3 -clock clk {surdbmux};
set_output_delay -max 4.3 -clock clk {surdamux};
set_output_delay -max 4.65 -clock clk {rd_offset};
set_output_delay -max 4.25 -clock clk {vu_comp_k};	/* really mb 5.0 */
set_output_delay -max 5.5 -clock clk {susltlt}; 
set_output_delay -max 6.5 -clock clk {surfile_ra_f}; 
set_output_delay -max 6.5 -clock clk {surfile_ra_t}; 
set_output_delay -max 6.5 -clock clk {surfile_rb_f}; 
set_output_delay -max 6.5 -clock clk {surfile_rb_t}; 
set_output_delay -max 7.3 -clock clk {suvulsoffsetmux};
set_output_delay -max 8.5 -clock clk {link_pc_delay_pc}; 
set_output_delay -max 7.3 -clock clk {suimmmux}; 
set_output_delay -max 8.5 -clock clk {vu_ld_addr};
set_output_delay -max 7.5 -clock clk {surfile_w_f};
set_output_delay -max 7.5 -clock clk {surfile_w_t};
set_output_delay -max 6.7 -clock clk {suimmlsmux}; 
set_output_delay -max 8.6 -clock clk {vu_st_addr};	/* s.b. 9.0 */
set_output_delay -max 9.0 -clock clk {xpose};		/* s.b. 9.5 */
set_output_delay -max 9.6 -clock clk {vu_st_xpose_addr}; /* s.b. 9.0 */
set_output_delay -max 10.5 -clock clk {ex_ctc2_vc0};
set_output_delay -max 10.5 -clock clk {ex_ctc2_vc1};
set_output_delay -max 10.5 -clock clk {ex_ctc2_vc2};
set_output_delay -max 9.5 -clock clk {rd_elem_num};
set_output_delay -max 10.5 -clock clk {sualuen};
set_output_delay -max 10.5 -clock clk {sushen};
set_output_delay -max 10.5 -clock clk {suslten}; 
set_output_delay -max 10.5 -clock clk {suwben}; 
set_output_delay -max 9.9 -clock clk {vu_elem};	/* really mb 9.0 */
set_output_delay -max 9.9 -clock clk {vu_func};    	/* really mb 9.0 */
set_output_delay -max 10.3 -clock clk {su_inst};
set_output_delay -max 12.5 -clock clk {acc_wr_en};
set_output_delay -max 12.5 -clock clk {acc_wr_reg}; 
set_output_delay -max 12.5 -clock clk {chip_sel}; 
set_output_delay -max 12.5 -clock clk {sushamux};
set_output_delay -max 12.5 -clock clk {sushbmux};
set_output_delay -max 10.35 -clock clk {vs}; 		/* s.b. 10.0 */
set_output_delay -max 12.5 -clock clk {imem_chip_sel_l};	
set_output_delay -max 13.5 -clock clk {imem_dma_cycle};
set_output_delay -max 13.5 -clock clk {sudrivels};
set_output_delay -max 13.5 -clock clk {sushift_s};
set_output_delay -max 13.6 -clock clk {cp0_enable}; 
set_output_delay -max 13.65 -clock clk {shiftamt};
set_output_delay -max 15.3 -clock clk {pc};
set_output_delay -max 15.5 -clock clk {cp0_address};
set_output_delay -max 15.5 -clock clk {cp0_write}; 
set_output_delay -max 15.5 -clock clk {sualuamux}; 
set_output_delay -max 15.5 -clock clk {sualubmux};
set_output_delay -max 15.5 -clock clk {sualu};
set_output_delay -max 16.0 -clock clk {df_ls_drive_ls_in_wb};
set_output_delay -max 16.0 -clock clk {df_pass_thru}; 
set_output_delay -max 16.0 -clock clk {elem_num};
set_output_delay -max 16.0 -clock clk {ex_cfc2};
set_output_delay -max 16.0 -clock clk {ex_mfc0};
set_output_delay -max 16.0 -clock clk {ex_mfc2};
set_output_delay -max 16.0 -clock clk {ex_mtc2};
set_output_delay -max 16.0 -clock clk {ex_su_byte_ls};
set_output_delay -max 16.0 -clock clk {ex_su_half_ls};
set_output_delay -max 16.0 -clock clk {ex_su_uns_ls};
set_output_delay -max 16.0 -clock clk {su_ex_load};
set_output_delay -max 16.0 -clock clk {su_ex_store};
set_output_delay -max 16.0 -clock clk {su_mem_wen}; 
set_output_delay -max 16.0 -clock clk {vu_ex_load};
set_output_delay -max 16.0 -clock clk {vu_ex_store};
set_output_delay -max 16.5 -clock clk {sualu_cin};
set_output_delay -max 17.0 -clock clk {rd_pre_vt};
set_output_delay -max 14.1 -clock clk {vt_sel};

set_load .7 {surfile_ra_t}; 
set_load .7 {surfile_ra_f}; 
set_load .7 {surfile_rb_t}; 
set_load .7 {surfile_rb_f}; 
set_load .7 {surdamux};
set_load .7 {surdbmux};
set_load .7 {suimmmux}; 
set_load .7 {suimmlsmux}; 
set_load .7 {suvulsoffsetmux};

set_load .7 {rd_base};
set_load .7 {rd_offset};
set_load .7 {rd_elem_num};
set_load .7 {vu_rd_ld_dec_k};
set_load .7 {vu_rd_st_dec_k};

set_load .7 {set_broke};

set_load .7 {sualuamux}; 
set_load .7 {sualubmux};
set_load .7 {sushamux};
set_load .7 {sushbmux};
set_load .7 {sudrivels};
set_load .7 {suslten}; 
set_load .7 {susltlt}; 
set_load .7 {sualuen};
set_load .7 {sualu};
set_load .7 {sushen};
set_load .7 {shiftamt};
set_load .7 {sushift_s};

set_load .7 {su_ex_store};
set_load .7 {su_ex_load};
set_load .7 {vu_ex_store};
set_load .7 {vu_ex_load};
set_load .7 {ex_mfc2};
set_load .7 {ex_mtc2};
set_load .7 {ex_cfc2};
set_load .7 {ex_su_byte_ls};
set_load .7 {ex_su_half_ls};
set_load .7 {ex_su_uns_ls};
set_load .7 {elem_num};
set_load .7 {chip_sel};
set_load .7 {df_ls_drive_ls_in_wb};
set_load .7 {df_pass_thru};

set_load .7 {surfile_w_t};
set_load .7 {surfile_w_f};
set_load .7 {su_mem_wen}; 
set_load .7 {suwben}; 
 
set_load 1.7 {vu_comp_k};
set_load 1.7 {vu_func};
set_load 1.7 {vs_eq_one};
set_load 1.7 {vu_elem};
set_load 1.7 {vs}; 
set_load 1.7 {vu_rd_store_type_k};
set_load 1.7 {vu_rd_storecfc2_k};
set_load 1.7 {rd_cfvc0_k};
set_load 1.7 {rd_cfvc1_k};
set_load 1.7 {rd_cfvc2_k};
set_load 1.7 {ex_ctc2_vc0};
set_load 1.7 {ex_ctc2_vc1};
set_load 1.7 {ex_ctc2_vc2};
set_load 1.7 {acc_wr_reg}; 
set_load 1.7 {acc_wr_en};
set_load 1.7 {vu_ld_addr};
set_load 1.7 {vu_st_addr};
set_load 1.7 {vu_st_xpose_addr};
set_load 1.7 {xpose};

set_load .7 {cp0_address}; 
set_load .7 {cp0_write}; 
set_load .7 {cp0_enable}; 
set_load .7 {ex_mfc0};
set_load .7 {imem_chip_sel_l};
set_load .7 {imem_dma_cycle};
set_load .7 {link_pc_delay_pc};
set_load .7 {pc};

set_max_transition 1.45 {vu_comp_k}
set_max_transition 1.45 {vu_func}
set_max_transition 1.45 {vs_eq_one}
set_max_transition 1.45 {vu_elem}
set_max_transition 1.45 {vs}
set_max_transition 1.45 {vu_rd_store_type_k}
set_max_transition 1.45 {vu_rd_storecfc2_k}
set_max_transition 1.45 {rd_cfvc0_k}
set_max_transition 1.45 {rd_cfvc1_k}
set_max_transition 1.45 {rd_cfvc2_k}
set_max_transition 1.45 {ex_ctc2_vc0}
set_max_transition 1.45 {ex_ctc2_vc1}
set_max_transition 1.45 {ex_ctc2_vc2}
set_max_transition 1.45 {acc_wr_reg}
set_max_transition 1.45 {acc_wr_en}
set_max_transition 1.45 {vu_ld_addr}
set_max_transition 1.45 {vu_st_addr}
set_max_transition 1.45 {vu_st_xpose_addr}
set_max_transition 1.45 {xpose}