create_clock clock -period 16.5 -waveform {0.0 8.25}


set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 3.6 -clock clk {su_inst_a};
set_input_delay 3.6 -clock clk {vu_inst_a};
set_input_delay 4.0 -clock clk {su_inst_b};
set_input_delay 4.0 -clock clk {vu_inst_b};
set_input_delay 4.3 -clock clk {choose_su_inst_b};	/* *** really 4.5 */
set_input_delay 4.3 -clock clk {choose_vu_inst_b};	/* *** really 4.5 */
set_input_delay 9.5 -clock clk {kill_re_non_vu};	/* *** really 10.5 ? */
set_input_delay 9.5 -clock clk {kill_su_issue};		/* *** really 10.5 */
set_input_delay 9.5 -clock clk {kill_vu_issue};		/* *** really 10.5 */
set_input_delay 2.0 -clock clk {elem_num};
set_input_delay 13.0 -clock clk {vu_comp_k};

set_output_delay -max 7.2 -clock clk {xpose};		/* *** really 9.5 */
set_output_delay -max 5.0 -clock clk {vu_reg_hazard_ls};
set_output_delay -max 5.0 -clock clk {vu_reg_hazard_comp};

set_output_delay -max 7.9 -clock clk {vu_func};		/* really mb 9.0 */
set_output_delay -max 7.9 -clock clk {vu_elem};		/* really mb 9.0 */
set_output_delay -max 6.5 -clock clk {vu_ld_addr};
set_output_delay -max 6.6 -clock clk {vu_st_addr};	/* really mb 9.0 */
set_output_delay -max 7.6 -clock clk {vu_st_xpose_addr}; /* really mb 9.0 */
set_output_delay -max 1.0 -clock clk {vu_rd_store_type_k};
set_output_delay -max 1.0 -clock clk {vu_rd_storecfc2_k};
set_output_delay -max 0.9 -clock clk {rd_cfvc0_k};
set_output_delay -max 0.9 -clock clk {rd_cfvc1_k};
set_output_delay -max 0.9 -clock clk {rd_cfvc2_k};
 
set_output_delay -max 8.5 -clock clk {ex_ctc2_vc0};
set_output_delay -max 8.5 -clock clk {ex_ctc2_vc1};
set_output_delay -max 8.5 -clock clk {ex_ctc2_vc2};
 
set_output_delay -max 10.5 -clock clk {acc_wr_reg}; 
set_output_delay -max 10.5 -clock clk {acc_wr_en};

set_load 1.7 {xpose};
set_load 1.7 {vu_func};
set_load 1.7 {vu_elem};
set_load 1.7 {vu_ld_addr};
set_load 1.7 {vu_st_addr};
set_load 1.7 {vu_st_xpose_addr};
set_load 1.7 {vu_rd_store_type_k};
set_load 1.7 {vu_rd_storecfc2_k};
set_load 1.7 {rd_cfvc0_k};
set_load 1.7 {rd_cfvc1_k};
set_load 1.7 {rd_cfvc2_k};
set_load 1.7 {ex_ctc2_vc0};
set_load 1.7 {ex_ctc2_vc1};
set_load 1.7 {ex_ctc2_vc2};
set_load 1.7 {acc_wr_reg}; 
set_load 1.7 {acc_wr_en};

set_max_transition 1.45 {xpose}
set_max_transition 1.45 {vu_func}
set_max_transition 1.45 {vu_elem}
set_max_transition 1.45 {vu_ld_addr}
set_max_transition 1.45 {vu_st_addr}
set_max_transition 1.45 {vu_st_xpose_addr}
set_max_transition 1.45 {vu_rd_store_type_k}
set_max_transition 1.45 {vu_rd_storecfc2_k}
set_max_transition 1.45 {rd_cfvc0_k}
set_max_transition 1.45 {rd_cfvc1_k}
set_max_transition 1.45 {rd_cfvc2_k}
set_max_transition 1.45 {ex_ctc2_vc0}
set_max_transition 1.45 {ex_ctc2_vc1}
set_max_transition 1.45 {ex_ctc2_vc2}
set_max_transition 1.45 {acc_wr_reg}
set_max_transition 1.45 {acc_wr_en}