module = iu

search_path = search_path + "../src" + "../inc" + \
   "../../lib/verilog/user" + "../syn"

/* read the compiled netlists */
read -f edif iu.edf_p
read -f edif ../su/syn/su.edf

current_design = iu

link 

set_dont_touch sudp

ungroup -flatten -all

check_design > iu.lint

set_wire_load 256000
set_operating_conditions NOM

set_driving_cell -cell in01d3 reset_l_0

set_max_transition 1.0 current_design

set_dont_touch { ne35hd130d/nt01d* }

compile -only_design_rule

report_constraint -verbose

/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy

/* standard reports & netlist */

include "report.dc"

write -f edif -o iu.edf -hier iu

quit