Makefile
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#
#####################################################
# Verilog source files #
#####################################################
SRCDIR = ../src
TC_SRCS= $(SRCDIR)/tc.v \
tc_adj.edf \
tc_adrs.edf \
tc_div.edf \
tc_frac.edf \
tc_lod.edf \
tc_sort.edf \
tc_tilemem.edf
default : tc.vsyn
tc.vsyn : tc.edf edf2vsyn.ss
dc_shell -f edf2vsyn.ss
tc.edf : tc.ss $(TC_SRCS)
dc_shell -f tc.ss | tee tc.synlog
tc_adj.edf: tc_adj.ss $(SRCDIR)/tc_adj.v
dc_shell -f tc_adj.ss | tee tc_adj.synlog
tc_adrs.edf: tc_adrs.ss $(SRCDIR)/tc_adrs.v
dc_shell -f tc_adrs.ss | tee tc_adrs.synlog
tc_div.edf: tc_div.ss $(SRCDIR)/tc_div.v
dc_shell -f tc_div.ss | tee tc_div.synlog
tc_frac.edf: tc_frac.ss $(SRCDIR)/tc_frac.v
dc_shell -f tc_frac.ss | tee tc_frac.synlog
tc_lod.edf: tc_lod.ss $(SRCDIR)/tc_lod.v
dc_shell -f tc_lod.ss | tee tc_lod.synlog
tc_sort.edf: tc_sort.ss $(SRCDIR)/tc_sort.v
dc_shell -f tc_sort.ss | tee tc_sort.synlog
tc_tilemem.edf: tc_tilemem.ss $(SRCDIR)/tc_tilemem.v
dc_shell -f tc_tilemem.ss | tee tc_tilemem.synlog
PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs
include $(PRDEPTH)/PRrules
LDIRT = *.log *.edf *.lint *.synlog *.vsyn