test.diag
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/*****************************************************************
* NORM state
*****************************************************************/
test = 0; pad_reset_l = 1; repeat (1) @(posedge clk);
#4; reset; repeat (4) @(posedge clk);
#4; pad_reset_l = 1; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h0;
ad16_enable_l = 0;
ad16_read_l = 0;
ad16_write_l = 0;
bist_flag = 1; repeat (2) @(posedge clk);
#4; ad16_enable_l = 1;
ad16_read_l = 1;
ad16_write_l = 1;
bist_flag = 0; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h7fff; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h0;
ad16_enable_l = 0; repeat (2) @(posedge clk);
/*****************************************************************
* MUX state
*****************************************************************/
#4; pad_reset_l = 0; repeat (2) @(posedge clk);
#4; test = 1; repeat (2) @(posedge clk);
repeat (4) @(posedge clk);
#4; next_state; repeat (4) @(posedge clk);
#4; ad16_enable_l = 0;
ad16_read_l = 0;
ad16_write_l = 0; repeat (2) @(posedge clk);
#4; ad16_enable_l = 1;
ad16_read_l = 1;
ad16_write_l = 1; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h1; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h2; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h4; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h8; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h10; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h20; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h40; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h80; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h100; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h200; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h400; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h800; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h1000; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'h2000; repeat (2) @(posedge clk);
#4; bist_flag = 1; repeat (2) @(posedge clk);
#4; bist_flag = 0; repeat (2) @(posedge clk);
#4; ad16_data_in = 15'hf; repeat (2) @(posedge clk);
/*****************************************************************
* BYP state
*****************************************************************/
repeat (4) @(posedge clk);
#4; next_state; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h3fff;
pad_reset_l = 0; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h5555;
pad_reset_l = 1; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h2222;
pad_reset_l = 0; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h4444;
pad_reset_l = 1; repeat (4) @(posedge clk);
#4; ad16_data_in = 15'h0;
pad_reset_l = 0; repeat (4) @(posedge clk);
#4; ad16_enable_l = 0;
ad16_read_l = 0;
ad16_write_l = 0; repeat (4) @(posedge clk);
#4; ad16_enable_l = 1;
ad16_read_l = 1;
ad16_write_l = 1; repeat (4) @(posedge clk);
#4; pad_reset_l = 1; repeat (6) @(posedge clk);
#4; ad16_enable_l = 0;
ad16_read_l = 0;
ad16_write_l = 0; repeat (4) @(posedge clk);
#4; ad16_enable_l = 1;
ad16_read_l = 1;
ad16_write_l = 1; repeat (4) @(posedge clk);
#4; test = 0; repeat (4) @(posedge clk);
#4; test = 1; repeat (4) @(posedge clk);
#4; test = 0; repeat (4) @(posedge clk);
#4; test = 1; repeat (4) @(posedge clk);
#4; test = 0; repeat (4) @(posedge clk);
#4; test = 1; repeat (4) @(posedge clk);