/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: tst.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $

////////////////////////////////////////////////////////////////////////
// Project Reality
// module: test controller
////////////////////////////////////////////////////////////////////////

module tst(
	  clock,
	  pad_reset_l,
	  test,
	  ad16_data_in,
	  tst_ad16_enable_l_0,
	  tst_ad16_enable_l_1,
	  tst_ad16_read_l,
	  tst_ad16_write_l,
	  ad16_enable_l,
	  ad16_read_l,
	  ad16_write_l,
	  //c_ctl_en,
	  //c_ctl_i,
	  //c_ctl_ld,
	  bist_flag,
	  tst_by_pass,
	  tst_bist_mode,
	  tst_iost_mode,
          tst_rac_reset,
          tst_ext_be,
	  tst_c_ctl_en,
	  tst_c_ctl_i,	
	  tst_c_ctl_ld,
	  tst_synclk_set,
	  tst_pwr_up,
	  tst_idd_test,
	  //
	  tst_reset_l_0,
	  tst_reset_l_1,
	  tst_reset_l_2,
	  tst_reset_l_3,
	  tst_reset_l_4,
	  tst_reset_l_5,
	  tst_reset_l_6,
	  tst_reset_l_7,
	  tst_reset_l_8,
	  tst_reset_l_9
	 );

input clock;
input pad_reset_l;
input test;

/* Cart. rom pad interface */
input [14:0] ad16_data_in; //** mapping **/ 
		           // 0 : ByPass
			   // 1 : SynClkSet
			   // 2 : BISTMode
			   // 3 : IOSTMode
			   // 4 : CCtli0
			   // 5 : CCtli1
			   // 6 : CCtli2
			   // 7 : CCtli3
			   // 8 : CCtli4
			   // 9 : CCtli5
			   //10 : CCtlEn
			   //11 : CCtlLd
			   //12 : RACReset
			   //13 : ExtBE
			   //14 : DelayIn

output tst_ad16_enable_l_0;
output tst_ad16_enable_l_1;
output tst_ad16_read_l;     // muxed !BISTFlag 
output tst_ad16_write_l;    // muxed  DelayOut

/*** pi block interface ***/
input ad16_enable_l;
input ad16_read_l;
input ad16_write_l;

/*** ri block interface ****/
wire       c_ctl_en = 1'b0;	 
wire [5:0] c_ctl_i  = 6'b0;
wire       c_ctl_ld = 1'b0;


/**** rac interface ********/
input  bist_flag;

output tst_by_pass;
output tst_bist_mode;
output tst_iost_mode;
output tst_rac_reset;
output tst_ext_be;

output       tst_c_ctl_en;
output [5:0] tst_c_ctl_i;
output       tst_c_ctl_ld;

output tst_synclk_set;

output tst_pwr_up;

/*** IDD test signal *****/
output tst_idd_test; 

/**** RCP reset fanout ****/
output tst_reset_l_0;
output tst_reset_l_1;
output tst_reset_l_2;
output tst_reset_l_3;
output tst_reset_l_4;
output tst_reset_l_5;
output tst_reset_l_6;
output tst_reset_l_7;
output tst_reset_l_8;
output tst_reset_l_9;


//////////////////////////////////////////////////////////////////

// reset_l input inverting buffer
in01d2  u_reset(.zn(reset), .i(pad_reset_l));

/***************************************************************
 * tst_state machine
 *
 *  00 : NORM
 *  01 : MUX
 *  11 : BYP
 *
 * @(posedge reset or negedge st_reset_l) st0 <= test | st0;
 * @(posedge reset or negedge st_reset_l) st1 <= (test&st0) | st1;
 *
 ***************************************************************/
wire st_0, st_1, stb_0, stb_1;

// st_reset_l = test | pad_reset_l;
or02d1	u_st_rst(.z(st_reset_l), .a1(test), .a2(pad_reset_l)); 
or02d1  u_st1p  (.z(st1_p),.a1(st_0), .a2(st_1));

mx21d1 u_st_0_p(.z(st_0_p), .i0(st_0), .i1(1'b1),  .s(test));
mx21d1 u_st_1_p(.z(st_1_p), .i0(st_1), .i1(st1_p), .s(test));

dfctnh  u_st0(.q(st_0), .qn(stb_0), .d(st_0_p), .cdn(st_reset_l), .cp(reset));
dfctnh  u_st1(.q(st_1), .qn(stb_1), .d(st_1_p), .cdn(st_reset_l), .cp(reset));

// MUX state
an02d2  u_muxb(.z(st_mux), .a1(st_0), .a2(stb_1));

/***************************************************************
 * tst_by_pass = (st0&ad16_data_in[0]) | st1; 
 *
 * tst_synclk_set = (st_mux) ? ad16_data_in[1] : 1'b1;
 * tst_bist_mode  = (st_mux) ? ad16_data_in[2] : 1'b0;
 * tst_iost_mode  = (st_mux) ? ad16_data_in[3] : 1'b0;
 *
 * tst_c_ctl_i[5:0] = (st_mux) ? ad16_data_in[9:4] : c_ctl_i[5:0];
 * tst_c_ctl_en     = (st_mux) ? ad16_data_in[1]   : c_ctl_en;
 * tst_c_ctl_ld     = (st_mux) ? ad16_data_in[1]   : c_ctl_ld;
 *
 * delay_in = ad16_data_in[12] & st_mux;
 *
 ***************************************************************/

//tst_by_pass = (st0 & in[0]) | st1;
nd02d1  u_in0b(.zn(in0b), .a1(ad16_data_in[0]), .a2(st_0));
nd02d2  u_by_pass_pre(.zn(tst_by_pass_pre), .a1(in0b), .a2(stb_1));
ni01d5  u_by_pass    (.z(tst_by_pass), .i(tst_by_pass_pre));

tst_mux21 u_tst_synclk_set(.z(tst_synclk_set),.i0(1'b1), .i1(ad16_data_in[1]), .s(st_mux));
tst_mux21 u_bist_mode_a   (.z(bist_mode_a), .i0(1'b0), .i1(ad16_data_in[2]), .s(st_mux));
tst_mux21 u_tst_iost_mode (.z(tst_iost_mode), .i0(1'b0), .i1(ad16_data_in[3]), .s(st_mux));

tst_mux21  u_tst_c_ctl_i0(.z(tst_c_ctl_i[0]),.i0(c_ctl_i[0]),  .i1(ad16_data_in[4]), .s(st_mux));
tst_mux21  u_tst_c_ctl_i1(.z(tst_c_ctl_i[1]),.i0(c_ctl_i[1]),  .i1(ad16_data_in[5]), .s(st_mux));
tst_mux21  u_tst_c_ctl_i2(.z(tst_c_ctl_i[2]),.i0(c_ctl_i[2]),  .i1(ad16_data_in[6]), .s(st_mux));
tst_mux21  u_tst_c_ctl_i3(.z(tst_c_ctl_i[3]),.i0(c_ctl_i[3]),  .i1(ad16_data_in[7]), .s(st_mux));
tst_mux21  u_tst_c_ctl_i4(.z(tst_c_ctl_i[4]),.i0(c_ctl_i[4]),  .i1(ad16_data_in[8]), .s(st_mux));
tst_mux21  u_tst_c_ctl_i5(.z(tst_c_ctl_i[5]),.i0(c_ctl_i[5]),  .i1(ad16_data_in[9]), .s(st_mux));
tst_mux21  u_tst_c_ctl_en(.z(tst_c_ctl_en),  .i0(c_ctl_en),    .i1(ad16_data_in[10]),.s(st_mux));
tst_mux21  u_tst_c_ctl_ld(.z(tst_c_ctl_ld),  .i0(c_ctl_ld),    .i1(ad16_data_in[11]),.s(st_mux));
tst_mux21  u_tst_rac_reset(.z(tst_rac_reset),.i0(tst_reset_pre),.i1(ad16_data_in[12]),.s(st_mux));
tst_mux21  u_tst_ext_be(.z(tst_ext_be),      .i0(1'b0),        .i1(ad16_data_in[13]),.s(st_mux));

an02d1  u_dlyin(.z(delay_in), .a1(ad16_data_in[14]), .a2(st_mux));

// RAC BIST syncronization
dfntnh  u_bist_mode_b   (.q(bist_mode_b),  .d(bist_mode_a), .cp(clock));
ni01d2  u_bist_mode_c   (.z(bist_mode_c),  .i(bist_mode_b)            );
lanfnh  u_bist_mode_d   (.q(bist_mode_d),  .d(bist_mode_c), .en(clock));
ni01d5  u_tst_bist_mode (.z(tst_bist_mode),.i(bist_mode_d)            );

/***************************************************************
 * tst_ad16_enable_l = (st1&reset) | st_mux | ad16_enable_l |  
 *
 * tst_ad16_read_l  = (st_mux) ? ~bist_flag : ad16_read_l;
 * tst_ad16_write_l = (st_mux) ? ~delay_out : ad16_write_l;
 *
 ***************************************************************/

ao05d1 u_tst_ad16_enable(.zn(tst_ad16_enable), 
	                .a1(st_1), .a2(reset),
	                .b(st_mux),
	                .c(ad16_enable_l)
	               );

// the following inverter gate causes verilog-VCS to go into infinite loop.
in01d5 u_tst_ad16_enable_l_0(.zn(tst_ad16_enable_l_0), .i(tst_ad16_enable));
in01d5 u_tst_ad16_enable_l_1(.zn(tst_ad16_enable_l_1), .i(tst_ad16_enable));

in01d1 u_bist_flag_l(.zn(bist_flag_l), .i(bist_flag));

mx21d2 u_tst_ad16_read_l_pre (.z(tst_ad16_read_l_pre ), .i0(ad16_read_l ), .i1(bist_flag_l),.s(st_mux));
mx21d2 u_tst_ad16_write_l_pre(.z(tst_ad16_write_l_pre), .i0(ad16_write_l), .i1(delay_out),  .s(st_mux));

ni01d5 u_tst_ad16_read_l (.z(tst_ad16_read_l ), .i(tst_ad16_read_l_pre )); 
ni01d5 u_tst_ad16_write_l(.z(tst_ad16_write_l), .i(tst_ad16_write_l_pre)); 


/***************************************************************
 * tst_pwr_up = test | !st1;
 * tst_idd_test = !tst_pwr_up;
 ***************************************************************/

or02d2 u_tst_pwr_up(.z(tst_pwr_up), .a1(test), .a2(stb_1));
in01d5 u_tst_idd_test(.zn(tst_idd_test), .i(tst_pwr_up));

/***************************************************************
 * Delay Block
 ***************************************************************/

wire [10:0] dlyout; 

tst_delay8  u_dly00(.z(dlyout[0]), .i(delay_in));
tst_delay8  u_dly01(.z(dlyout[1]), .i(dlyout[0]));
tst_delay8  u_dly02(.z(dlyout[2]), .i(dlyout[1]));
tst_delay8  u_dly03(.z(dlyout[3]), .i(dlyout[2]));
tst_delay8  u_dly04(.z(dlyout[4]), .i(dlyout[3]));
tst_delay8  u_dly05(.z(dlyout[5]), .i(dlyout[4]));
tst_delay8  u_dly06(.z(dlyout[6]), .i(dlyout[5]));
tst_delay8  u_dly07(.z(dlyout[7]), .i(dlyout[6]));
tst_delay8  u_dly08(.z(dlyout[8]), .i(dlyout[7]));
tst_delay8  u_dly09(.z(dlyout[9]), .i(dlyout[8]));
tst_delay8  u_dly10(.z(dlyout[10]),.i(dlyout[9]));
tst_delay8  u_dly11(.z(delay_out ),.i(dlyout[10]));


/*****************************************************************
 * Reset Syncronizer and buffer for rest of the chip
 *****************************************************************/

dfctnh  u_rst1(.q(pad_rst_l_d1),.d(pad_reset_l), .cdn(pad_reset_l),.cp(clock));
dfctnh  u_rst2(.q(pad_rst_sync),.d(pad_rst_l_d1),.cdn(pad_reset_l),.cp(clock));

in01d5 u_rstbuf_pre(.zn(tst_reset_pre), .i(pad_rst_sync));

in01d5 u_rstbuf00(.zn(tst_reset_l_0), .i(tst_reset_pre));
in01d5 u_rstbuf10(.zn(tst_reset_l_1), .i(tst_reset_pre));
in01d5 u_rstbuf20(.zn(tst_reset_l_2), .i(tst_reset_pre));
in01d5 u_rstbuf30(.zn(tst_reset_l_3), .i(tst_reset_pre));
in01d5 u_rstbuf40(.zn(tst_reset_l_4), .i(tst_reset_pre));
in01d5 u_rstbuf50(.zn(tst_reset_l_5), .i(tst_reset_pre));
in01d5 u_rstbuf60(.zn(tst_reset_l_6), .i(tst_reset_pre));
in01d5 u_rstbuf70(.zn(tst_reset_l_7), .i(tst_reset_pre));
in01d5 u_rstbuf80(.zn(tst_reset_l_8), .i(tst_reset_pre));
in01d5 u_rstbuf90(.zn(tst_reset_l_9), .i(tst_reset_pre));

endmodule

/***********************************************************************/
/***********************************************************************/
/***********************************************************************/

// function z = (s) ? i1 : i0; 
module tst_mux21(i0,i1,z,s);
input i0,i1,s; 
output z;

in01d1  u_s0(.zn(s0),.i(s));

in01d1  u_s0b(.zn(s0b),.i(s0));
in01d1  u_s0x(.zn(s0x),.i(s0b));
nd02d1  u_s1 (.zn(s1), .a1(s0x), .a2(s0x));

nd02d1  u_i0b(.zn(i0b), .a1(i0), .a2(s0));
nd02d1  u_i1b(.zn(i1b), .a1(i1), .a2(s1));

nd02d2  u_z_pre(.zn(z_pre), .a1(i0b), .a2(i1b));

ni01d5  u_z(.z(z), .i(z_pre));

endmodule

/////////////////////////////////////////////
// Inverter chain of 8-inv
module tst_delay8(z,i);
input  i;
output z;

wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;

assign z = n_7;

// chain
in01d1 u00(.zn(n_0), .i(i));
in01d1 u01(.zn(n_1), .i(n_0));
in01d1 u02(.zn(n_2), .i(n_1));
in01d1 u03(.zn(n_3), .i(n_2));
in01d1 u04(.zn(n_4), .i(n_3));
in01d1 u05(.zn(n_5), .i(n_4));
in01d1 u06(.zn(n_6), .i(n_5));
in01d1 u07(.zn(n_7), .i(n_6));

// Loads
in01d1 u_l0_0(.i(n_0));

in01d1 u_l1_0(.i(n_1));
in01d1 u_l1_1(.i(n_1));

in01d1 u_l2_0(.i(n_2));
in01d1 u_l2_1(.i(n_2));
in01d1 u_l2_2(.i(n_2));

in01d1 u_l3_0(.i(n_3));
in01d1 u_l3_1(.i(n_3));
in01d1 u_l3_2(.i(n_3));
in01d1 u_l3_3(.i(n_3));

in01d1 u_l4_0(.i(n_4));
in01d1 u_l4_1(.i(n_4));
in01d1 u_l4_2(.i(n_4));
in01d1 u_l4_3(.i(n_4));
in01d1 u_l4_4(.i(n_4));

in01d1 u_l5_0(.i(n_5));
in01d1 u_l5_1(.i(n_5));
in01d1 u_l5_2(.i(n_5));
in01d1 u_l5_3(.i(n_5));
in01d1 u_l5_4(.i(n_5));
in01d1 u_l5_5(.i(n_5));

in01d1 u_l6_0(.i(n_6));
in01d1 u_l6_1(.i(n_6));
in01d1 u_l6_2(.i(n_6));
in01d1 u_l6_3(.i(n_6));
in01d1 u_l6_4(.i(n_6));
in01d1 u_l6_5(.i(n_6));
in01d1 u_l6_6(.i(n_6));

in01d1 u_l7_0(.i(n_7));
in01d1 u_l7_1(.i(n_7));
in01d1 u_l7_2(.i(n_7));
in01d1 u_l7_3(.i(n_7));
in01d1 u_l7_4(.i(n_7));
in01d1 u_l7_5(.i(n_7));
in01d1 u_l7_6(.i(n_7));
in01d1 u_l7_7(.i(n_7));
endmodule