Makefile 2 KB
# #!smake -J4
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#  Verilog source files                             #
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SRCDIR  = ../src
INCDIR  = ../../inc
LIBDIR  = ../../../lib/verilog/user

INC_SRCS =      $(INCDIR)/vi.vh \
                $(INCDIR)/rcp.vh \
                $(INCDIR)/reality.vh

VI_SRCS =	../src/vi.v \
		vi_dma.edf \
		vi_controller.edf \
		vi_sync.edf \
		vi_pipe.edf \
		vi_rand.edf

VIP_SRCS =	../src/vi_pipe.v \
		vi_filter.edf \
		vi_lerp.edf \
		vi_divot.edf \
		vi_gamma.edf

VIF_SRCS =	../src/vi_filter_csa.v \
		../src/vi_filter_and.v \
		../src/vi_filter_csa_add8.v \
		../src/vi_filter_csa_and.v \
		../src/vi_filter_csa_fa7.v \
		../src/vi_filter_csa_fa8.v \
		../src/vi_filter_csa_faso.v \
		../src/vi_filter_csa_faco.v \
		../src/vi_filter_csa_ha1.v \
		../src/vi_filter_csa_haso.v \
		../src/vi_filter_csa_haco.v \
		../src/vi_filter_csa_nand.v \
		../src/vi_filter_max.v \
		../src/vi_filter_penult.v \
		../src/vi_filter.v

VIL_SRCS =	../src/vi_lerp.v \
		../src/vi_lerp_booth.v \
		../src/vi_lerp_booth0.v \
		../src/vi_lerp_booth7.v \
		../src/vi_lerp_csa.v \
		../src/vi_lerp_csa_add10.v \
		../src/vi_lerp_csa_fa4.v \
		../src/vi_lerp_csa_fa5.v \
		../src/vi_lerp_csa_fa6.v \
		../src/vi_lerp_csa_ha1.v \
		../src/vi_lerp_csa_ha2.v \
		../src/vi_lerp_csa_ha3.v \
		../src/vi_lerp_csa_haco.v \
		../src/vi_lerp_csa_haso.v

default			: vi.edf vi.vsyn

vi.edf			: $(VI_SRCS) $(INC_SRCS)
vi_dma.edf		: ../src/vi_dma.v $(LIBDIR)/cbus_driver.v $(INC_SRCS)
vi_controller.edf	: ../src/vi_controller.v $(INC_SRCS)
vi_sync_fsm.edf		: ../src/vi_sync_fsm.v
vi_sync.edf		: ../src/vi_sync.v vi_sync_fsm.edf
vi_pipe.edf		: $(VIP_SRCS)
vi_rand.edf		: ../src/vi_rand.v
vi_filter.edf		: $(VIF_SRCS)
vi_lerp.edf		: $(VIL_SRCS)
vi_divot.edf		: ../src/vi_divot.v ../src/vi_divot_median.v
vi_gamma.edf		: ../src/vi_gamma.v ../src/vi_gamma_sqrt.v

PRDEPTH=../../../../..
include $(PRDEPTH)/PRdefs 
include $(PRDEPTH)/PRrules 
LDIRT = *.log *.edf *.lint *.synlog *.vsyn