module div(CLK, Reset_l, OpCode, OpCodeValid, VTL, VTH, El2, DivOut);

input CLK;
input Reset_l;
input [5:0] OpCode;
input OpCodeValid;
input [15:0] VTH;                       // Scalar Value from Elements(4:7)
input [15:0] VTL;                       // Scalar Value from Elements(0:3)
input El2;                              // Element bit 2

output [15:0] DivOut;

/******************************************************/

wire [15:0] ROMData;
wire [9:0] RADDR;
wire ROMCLK;

div_rom udivrom(.oe(1'b1), .clk(ROMCLK), .a(RADDR), .out(ROMData)); 
divctl  udivctl(.CLK(CLK), 
	        .Reset_l(Reset_l), 
	        .OpCode(OpCode), 
	        .OpCodeValid(OpCodeValid), 
	        .VTL(VTL), 
	        .VTH(VTH), 
	        .El2(El2), 
	        .ROMData(ROMData), 
	        .RADDR(RADDR), 
	        .DivOut(DivOut),
	        .ROMCLK(ROMCLK)
               );
endmodule