vmult.ss
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alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 14.0 -waveform {0 7.0}; \
set_input_delay 6.0 -clock clk all_inputs(); \
set_output_delay 4.0 -clock clk all_outputs(); \
set_driving_cell -none {clk}; \
set_driving_cell -cell in01d0 all_inputs(); \
set_drive 0 {clk}; \
set_load 1.0 all_outputs();"
/* read the verilog sources */
read -f verilog ../src/vmult.v
current_design = vmult
ungroup -flatten csa_*
ungroup -flatten ha_*
ungroup -flatten cla
dont_touch csa_*
dont_touch ha_*
dont_touch cla*
max_fanout 16
set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.0 current_design;
link
check_design > vmult.lint
compile -map_effort high -incremental_mapping
compile -map_effort high -incremental_mapping
report -reference > report/vmult.ref
report_constraint -all_violators > report/vmult.violators
report_timing -path full -delay max -max_paths 10 > report/vmult.full.paths
write -f edif -o vmult.edf -hier vmult
quit