set_dont_touch vuctl
set_dont_touch vudp
set_dont_touch vmult

current_design = vusl

set_input_delay 4 -clock clk {reset_l};
set_max_fanout 0.02 {reset_l};

set_input_delay 12 -clock clk {su_instvld_rd};
set_input_delay 10 -clock clk {su_storeinst_rd};
set_input_delay 10 -clock clk {su_storecfc2_rd};
set_input_delay 10 -clock clk {su_vseqone_rd};
set_input_delay 8 -clock clk {su_instelem_rd};
set_input_delay 8 -clock clk {su_instfunc_rd};
set_input_delay 10 -clock clk {su_rdcmpcd_rd};
set_input_delay 10 -clock clk {su_rdcryout_rd};
set_input_delay 10 -clock clk {su_rdcmpcdad_rd};
set_input_delay 8 -clock clk {su_wrcmpcd_wb};
set_input_delay 8 -clock clk {su_wrcryout_wb};
set_input_delay 8 -clock clk {su_wrcmpcdad_wb};


set_input_delay 7 -clock clk {su_st_rnum_rd};
set_input_delay 7 -clock clk {su_xp_rnum_rd};
set_input_delay 7 -clock clk {su_ld_rnum_ac};


set_input_delay 6 -clock clk {su_vs_addr_rd};
set_input_delay 5 -clock clk {su_vt_addr_rd};
set_input_delay 13 -clock clk {su_vd_addr_ac};
set_input_delay 13 -clock clk {su_wbv_wr_en_ac};
set_input_delay 13 -clock clk {su_bwe_ac};
set_input_delay 8 -clock clk {su_xposeop_rdac};
set_drive 0 {vct_slice0};
set_input_delay 0.0 -clock clk {vct_slice0};
set_drive 0 {vct_slice1};
set_input_delay 0.0 -clock clk {vct_slice1};

set_input_delay 8 -clock clk {vdi_divrslt_wb};
set_input_delay 8 -clock clk {vdp_hlfin_rd};
set_input_delay 10 -clock clk {vdp_whlin_rd};
set_input_delay 10 -clock clk {vct_hlfsl_rd};
set_input_delay 12 -clock clk {vct_whlsl_rd};

set_input_delay 4 -clock clk {vdp_datatristen0_mu};
set_input_delay 4 -clock clk {vdp_datatristen1_mu};

set_output_delay -max 3 -clock clk {vct_hlflosl_rd};
set_output_delay -max 2 -clock clk {vct_whllosl_rd};
set_output_delay -max 3 -clock clk {vct_hlfhisl_rd};
set_output_delay -max 2 -clock clk {vct_whlhisl_rd};

set_output_delay -max 3 -clock clk {vdp_hlfout_rd};
set_output_delay -max 2 -clock clk {vdp_whlout_rd};

set_output_delay -max 2 -clock clk {su_storeinst_mu};
set_output_delay -max 2 -clock clk {su_storecfc2_mu};

set_input_delay 10 -clock clk {su_cont_to_from};
set_output_delay -max 4.0 -clock clk {su_cont_to_from};

set_input_delay 4 -clock clk {su_data_to_from};
set_output_delay -max 4 -clock clk {su_data_to_from};