dramadr0.tdf
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TITLE "$Id: dramadr0.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc. ";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, 1995 Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
INCLUDE "rcpproto.inc";
subdesign dramadr0
(
%gio%
gio_clk2, % freq doubled, phase locked version of gio_clk %
gio_oeB, % output enable for gio bus %
gio_cntl[2..0] % control for gio bus transactions %
: INPUT;
% address/data bus from gio interface transceiver %
gio_adh[19..12], gio_adl[3..0] : BIDIR;
%ad16 (cart)%
carry_in, % address adder carry from other address chip %
cart_oeB, % output enable for cartridge bus %
cart_cntl[2..0] % control for cartridge bus transactions %
: INPUT;
carry_out % address adder carry to other address chip %
: OUTPUT;
% cartridge address-data bus %
ad16_adh[15..12], ad16_adl[3..0] : BIDIR;
%dram%
% control for dram addresses %
dr0_cntl[2..0], dr1_cntl[2..0] : INPUT;
% address buses for dram banks %
dr0_adr[11..6], dr1_adr[11..6] : OUTPUT;
)
variable
clock, carry_out : NODE;
gio_out[3..0], inc_cart, inc_cart1, dly_alel,
cart_adl[3..0], cart_adrla[15..12],
cart_adrlb[2..1], dr0_adr[11..6], dr1_adr[11..6] : dff;
gio_int[3..0], cart_int[3..0], cart_adrh[19..16],
gio_adrh[19..12], gio_adrl[2..1] : dffe;
gio_adh[19..12], gio_adl[3..0], ad16_adh[15..12], ad16_adl[3..0] : tri;
begin
clock = global(gio_clk2); % 66 MHz clock %
% gio bus registers %
gio_adrh[].clk = clock;
gio_adrh[].ena = (gio_cntl[] == GIO_VADR);
gio_adrh[] = gio_adh[];
gio_adrl[].clk = clock;
gio_adrl[].ena = (gio_cntl[] == GIO_VADR);
gio_adrl[] = gio_adl[2..1];
cart_int[].clk = clock;
cart_int[].ena = (gio_cntl[] == WR_CART_INT);
cart_int[] = gio_adl[];
gio_adh[].oe = !gio_oeB;
gio_adh[] = 0;
gio_adl[].oe = !gio_oeB;
gio_adl[] = gio_out[];
gio_out[].clk = clock;
case gio_cntl[] is
when GRD_CART_INT => gio_out[] = cart_int[];
when GRD_GIO_INT => gio_out[] = gio_int[];
when RD_GIO_PAGE => gio_out[] = 0;
when RD_GIO_ID => gio_out[] = 5;
when OTHERS => gio_out[] = gio_out[];
end case;
% cartridge bus registers %
cart_adrh[].clk = clock;
cart_adrh[].ena = (cart_cntl[] == CART_ALEH);
cart_adrh[] = ad16_adl[];
inc_cart.clk = clock;
inc_cart = (dr0_cntl[] == CART_CAS1) # (dr1_cntl[] == CART_CAS1);
inc_cart1.clk = clock;
inc_cart1 = (dr1_cntl[] == CART_CAS1);
dly_alel.clk = clock;
dly_alel = (cart_cntl[] == CART_ALEL);
cart_adrla[].clk = clock;
if (inc_cart1) then
if (carry_in) then
cart_adrla[] = cart_adrla[] + 1;
else
cart_adrla[] = cart_adrla[];
end if;
elsif (dly_alel) then
cart_adrla[] = ad16_adh[];
else
cart_adrla[] = cart_adrla[];
end if;
cart_adrlb[].clk = clock;
if (inc_cart) then cart_adrlb[] = 0;
elsif (dly_alel) then cart_adrlb[] = ad16_adl[2..1];
else cart_adrlb[] = cart_adrlb[];
end if;
% outputs to cartridge bus %
ad16_adh[].oe = !cart_oeB;
ad16_adh[] = 0;
ad16_adl[].oe = !cart_oeB;
ad16_adl[] = cart_adl[];
cart_adl[].clk = clock;
case cart_cntl[] is
when CRD_CART_INT => cart_adl[] = cart_int[];
when CRD_GIO_INT => cart_adl[] = gio_int[];
when CRD_ZERO => cart_adl[] = 0;
when OTHERS => cart_adl[] = cart_adl[];
end case;
gio_int[].clk = clock;
gio_int[].ena = (cart_cntl[] == WR_GIO_INT);
gio_int[] = ad16_adl[];
carry_out = gnd;
dr0_adr[].clk = clock;
case dr0_cntl[] is
when GIO_RAS => dr0_adr[] = gio_adrh[19..14];
when GIO_CAS1 => dr0_adr[] = (B"00", gio_adrh[13..12], gio_adrl[2..1]);
when CART_RAS => dr0_adr[] = (cart_adrh[], cart_adrla[15..14]);
when CART_CAS1 => dr0_adr[] = (B"00", cart_adrla[13..12], cart_adrlb[]);
when CART_CAS2, GIO_CAS2 =>
dr0_adr[11..8] = dr0_adr[11..8];
dr0_adr[7..6] = dr0_adr[7..6] + 1;
when OTHERS => dr0_adr[] = dr0_adr[];
end case;
dr1_adr[].clk = clock;
case dr1_cntl[] is
when GIO_RAS => dr1_adr[] = gio_adrh[19..14];
when GIO_CAS1 => dr1_adr[] = (B"00", gio_adrh[13..12], gio_adrl[2..1]);
when CART_RAS => dr1_adr[] = (cart_adrh[], cart_adrla[15..14]);
when CART_CAS1 => dr1_adr[] = (B"00", cart_adrla[13..12], cart_adrlb[]);
when CART_CAS2, GIO_CAS2 =>
dr1_adr[11..8] = dr1_adr[11..8];
dr1_adr[7..6] = dr1_adr[7..6] + 1;
when OTHERS => dr1_adr[] = dr1_adr[];
end case;
end;