dramadr1.tdf
5.03 KB
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TITLE "$Id: dramadr1.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc.";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, 1995 Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
INCLUDE "rcpproto.inc";
subdesign dramadr1
(
%gio%
gio_clk2, % freq doubled, phase locked version of gio_clk %
gio_oeB, % output enable for gio bus %
gio_cntl[2..0] % control for gio bus transactions %
: INPUT;
% address/data bus from gio interface transceiver %
gio_adh[23..20], gio_adl[11..4] : BIDIR;
%ad16 (cart)%
carry_in, % address adder carry from other address chip %
cart_oeB, % output enable for cartridge bus %
cart_cntl[2..0] % control for cartridge bus transactions %
: INPUT;
carry_out % address adder carry to other address chip %
: OUTPUT;
% cartridge address-data bus %
ad16_ad[11..4] : BIDIR;
%dram%
% control for dram addresses %
dr0_cntl[2..0], dr1_cntl[2..0] : INPUT;
% address buses for dram banks %
dr0_adr[5..0], dr1_adr[5..0] : OUTPUT;
)
variable
clock : NODE;
gio_outh[23..20], gio_outl[11..4], inc_cart, ena_cartl,
cart_ad[11..4], dr0_adr[5..0], dr1_adr[5..0], carry_out : dff;
g_active, gio_int[4], c_active, cart_int[4], cart_adrh[23..20],
cart_adrl[11..4], gio_page[23..20], gio_adr[11..4] : dffe;
gio_adh[23..20], gio_adl[11..4], ad16_ad[11..4] : tri;
begin
clock = global(gio_clk2); % 66 MHz clock %
% gio bus registers %
gio_page[].clk = clock;
gio_page[].ena = (gio_cntl[] == WR_GIO_PAGE);
gio_page[] = gio_adh[];
c_active.clk = clock;
c_active = (cart_cntl[] != CRD_CART_INT)
& ((gio_cntl[] == WR_CART_INT) # c_active);
cart_int[].clk = clock;
cart_int[].ena = (gio_cntl[] == WR_CART_INT);
cart_int[] = gio_adl[4];
gio_adr[].clk = clock;
gio_adr[].ena = (gio_cntl[] == GIO_VADR);
gio_adr[] = gio_adl[];
gio_adh[].oe = !gio_oeB;
gio_adh[] = gio_outh[];
gio_adl[].oe = !gio_oeB;
gio_adl[] = gio_outl[];
gio_outh[].clk = clock;
gio_outl[].clk = clock;
case gio_cntl[] is
when GRD_CART_INT =>
gio_outh[] = 0;
gio_outl[] = (c_active, B"000000", cart_int[]);
when GRD_GIO_INT =>
gio_outh[] = 0;
gio_outl[] = (g_active, B"000000", gio_int[]);
when RD_GIO_PAGE =>
gio_outh[] = gio_page[];
gio_outl[] = 0;
when RD_GIO_ID =>
gio_outh[] = 0;
gio_outl[] = 1;
when OTHERS =>
gio_outh[] = gio_outh[];
gio_outl[] = gio_outl[];
end case;
% cartridge bus registers %
g_active.clk = clock;
g_active = (gio_cntl[] != GRD_GIO_INT)
& ((cart_cntl[] == WR_GIO_INT) # g_active);
gio_int[].clk = clock;
gio_int[].ena = (cart_cntl[] == WR_GIO_INT);
gio_int[] = ad16_ad[4];
cart_adrh[].clk = clock;
cart_adrh[].ena = (cart_cntl[] == CART_ALEH);
cart_adrh[] = ad16_ad[7..4];
inc_cart.clk = clock;
inc_cart = (dr1_cntl[] == CART_CAS1);
ena_cartl.clk = clock;
ena_cartl = (dr1_cntl[] == CART_CAS1) # (cart_cntl[] == CART_ALEL);
cart_adrl[].clk = clock;
cart_adrl[].ena = ena_cartl;
if (inc_cart) then
cart_adrl[] = cart_adrl[] + 1;
else
cart_adrl[] = ad16_ad[];
end if;
% outputs to cartridge bus %
ad16_ad[].oe = !cart_oeB;
ad16_ad[] = cart_ad[];
cart_ad[].clk = clock;
case cart_cntl[] is
when CRD_CART_INT => cart_ad[] = (c_active,B"000000",cart_int[]);
when CRD_GIO_INT => cart_ad[] = (g_active,B"000000",gio_int[]);
when CRD_ZERO => cart_ad[] = 0;
when OTHERS => cart_ad[] = cart_ad[];
end case;
carry_out.clk = clock;
carry_out = (cart_adrl[] == H"ff");
dr0_adr[].clk = clock;
case dr0_cntl[] is
when GIO_RAS => dr0_adr[] = (gio_page[], gio_adr[11..10]);
when GIO_CAS1 => dr0_adr[] = gio_adr[9..4];
when CART_RAS => dr0_adr[] = (cart_adrh[], cart_adrl[11..10]);
when CART_CAS1 => dr0_adr[] = cart_adrl[9..4];
when OTHERS => dr0_adr[] = dr0_adr[];
end case;
dr1_adr[].clk = clock;
case dr1_cntl[] is
when GIO_RAS => dr1_adr[] = (gio_page[], gio_adr[11..10]);
when GIO_CAS1 => dr1_adr[] = gio_adr[9..4];
when CART_RAS => dr1_adr[] = (cart_adrh[], cart_adrl[11..10]);
when CART_CAS1 => dr1_adr[] = cart_adrl[9..4];
when OTHERS => dr1_adr[] = dr1_adr[];
end case;
end;