/**************************************************************/
/*    Verilog module of datapath cell dpcef001              */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Chunling Liu    Compass      June 11, 92 */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        X    : the input port                               */
/*        MSB  : the output port                              */
/*        LSB  : the output port                              */
/*    Parameters                                              */
/*        WORDSIZE   : the word size of the datapath cell     */
/*        Y_Bus_Size    : the word size of the datapath cell  */
/*        Coefficient:  constant defined by users             */
/*        DELAY      : the delay time from input to output    */
/**************************************************************/
module dpcef001(X, MSB, LSB);

  parameter WORDSIZE = 8, Y_Bus_Size = 7, Coefficient = 'b11111111, DELAY = 30, BF = 0;
  input  [WORDSIZE-1:0] X;
  output [WORDSIZE-1:0] MSB, LSB;

  function [2*WORDSIZE-1:0] mlt;
    input [WORDSIZE-1:0] x;

    reg [WORDSIZE+Y_Bus_Size-1:0] z;
    reg [Y_Bus_Size-1:0] y1;
    reg [WORDSIZE-1:0] y;
    integer i;
    begin
      mlt = {WORDSIZE+Y_Bus_Size{1'b0}};
      y1 = Coefficient;
      z = x * y1;
      if (WORDSIZE > Y_Bus_Size)
        begin
        mlt[Y_Bus_Size-1:0] = z[Y_Bus_Size-1:0];
        end
      else
        mlt[WORDSIZE-1:0] = z[Y_Bus_Size-1:0];
      mlt[2*WORDSIZE-1:WORDSIZE] = z[WORDSIZE+Y_Bus_Size-1:Y_Bus_Size];
    end
  endfunction

  assign #DELAY {MSB, LSB} = mlt(X);

endmodule