dpcef003.vmd
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/**************************************************************/
/* Verilog module of datapath cell dpcef003 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Chunling Liu Compass June 11, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* MSB : the output port */
/* LSB : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Y_Bus_Size : the word size of the datapath cell */
/* Coefficient: constant defined by users */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpcef003(X, MSB, LSB);
parameter WORDSIZE = 8, Y_Bus_Size = 7, Coefficient = 'b11111111, DELAY = 30, BF = 0;
input [WORDSIZE-1:0] X;
output [WORDSIZE-1:0] MSB, LSB;
function [2*WORDSIZE-1:0] mlt;
input [WORDSIZE-1:0] x;
reg [WORDSIZE+Y_Bus_Size-1:0] a;
reg [WORDSIZE-1:0] sx;
reg [Y_Bus_Size-1:0] sy;
reg [WORDSIZE-1:0] y;
begin
y = {{WORDSIZE-Y_Bus_Size{1'b0}},Coefficient};
if (x[WORDSIZE-1]^y[Y_Bus_Size-1])
begin
if (x[WORDSIZE-1] == 1)
begin
sx = ~x + 1;
sy = y;
end
else if (y[Y_Bus_Size-1] == 1)
begin
sx = x;
sy = ~y + 1;
end
a = ~(sx * sy) + 1;
end
else if (x[WORDSIZE-1]^~ y[Y_Bus_Size-1])
begin
if(x[WORDSIZE-1])
begin
sx = ~x + 1;
sy = ~y + 1;
end
else
begin
sx = x;
sy = y;
end
a = sx * sy;
end
else
a = {WORDSIZE+Y_Bus_Size{1'bx}};
mlt[WORDSIZE-1:0] = {{WORDSIZE-Y_Bus_Size{1'b0}},a[Y_Bus_Size-1:0]};
mlt[2*WORDSIZE-1:WORDSIZE] = a[WORDSIZE+Y_Bus_Size-1:Y_Bus_Size];
end
endfunction
assign #DELAY {MSB, LSB} = mlt(X);
endmodule