/**************************************************************/
/*    Verilog module of datapath cell DPCLKCKT0               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu     July, 1992               */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        CLK   : the input port                              */
/*        C     : the output port                             */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkckt0 (CLK, C);

  parameter DELAY = 3;
  input  CLK;
  output C;
  wire   #DELAY C = ~(~CLK);

endmodule