/**************************************************************/
/*    Verilog module of datapath cell DPCLKUCFV               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      Dec., 1992              */
/*                                                            */
/*    This module is added for the use of Verilog software    */
/*    compiler. It is not a cell in datapath.                 */
/*                                                            */
/*    The following is the port description                   */
/*    Control ports                                           */
/*        CLK     : the input port                              */
/*        CN    : the output port                             */
/*    Parameters                                              */
/*        DELAY     : the delay time from input to output     */
/**************************************************************/
module dpclkucfv (CLK, CN);

  parameter WORDSIZE = 1, DELAY = 3;
  input [WORDSIZE-1:0] CLK;
  output [WORDSIZE-1:0] CN;
  wire [WORDSIZE-1:0] #DELAY CN = ~CLK;

endmodule