dpfif000m.vmd
6.67 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/**************************************************************/
/* Verilog module of datapath cell DPFIF000M */
/* Designed by Lin Yang VLSI Technology Nov. 7, 90 */
/* */
/* The following is the port description */
/* Data ports */
/* I : the input port */
/* O : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST_CDN : the clear signal */
/* INST_WRN : the write signal */
/* INST_RDN : the read signal */
/* INST_FLAG1BAR : the first user flag */
/* INST_FLAG2BAR : the second user flag */
/* INST_EMPTYBAR : the empty flag */
/* INST_FULLBAR : the full flag */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Number_of_Words : the column size of the datapath cell */
/* FLAG1_Location : the first user flag location */
/* FLAG2_Location : the second user flag location */
/* DELAY : the delay time from input to output */
/* */
/* The output is triggered when the clock signal changes */
/* from 0 to 1, or unknown to 1. */
/**************************************************************/
module dpfif000m(I, O, INST_CP, INST_CDN, INST_WRN, INST_RDN,
INST_FLAG1BAR, INST_FLAG2BAR, INST_EMPTYBAR,
INST_FULLBAR);
parameter WORDSIZE = 8, Number_of_Words = 2,
FLAG1_Location = 1, FLAG2_Location = 1,
DELAY = 10, BF = 1;
input [WORDSIZE-1:0] I;
output [WORDSIZE-1:0] O;
input INST_CP, INST_CDN, INST_WRN, INST_RDN;
output INST_FLAG1BAR, INST_FLAG2BAR;
output INST_EMPTYBAR, INST_FULLBAR;
reg [WORDSIZE-1:0] O;
reg cp;
reg INST_FLAG1BAR, INST_FLAG2BAR;
reg INST_EMPTYBAR, INST_FULLBAR;
reg [WORDSIZE-1:0] rgf [Number_of_Words-1:0];
reg empty, full;
reg [WORDSIZE-1:0] tmp;
integer write_p, read_p, filled;
initial
begin
empty = 1;
full = 0;
write_p = 0;
read_p = 0;
filled = 0;
INST_FLAG1BAR = 1;
INST_FLAG2BAR = 1;
INST_EMPTYBAR = 1;
INST_FULLBAR = 1;
O = {WORDSIZE{1'b x}};
end
always @ ( posedge INST_CP )
begin
if (cp)
begin
if (INST_CDN)
begin
if (!INST_WRN & !INST_RDN)
begin
if (empty)
begin
rgf[write_p] = I;
write_p = (write_p+1) % Number_of_Words;
filled = 1;
$display("empty_filled = %d", filled);
end
else
begin
rgf[write_p] = I;
tmp = rgf[read_p];
$display("1_read_p = %d", read_p);
write_p = (write_p + 1) % Number_of_Words;
read_p = (read_p + 1) % Number_of_Words;
end
end
else if ( !INST_WRN & INST_RDN)
begin
if (!full)
begin
rgf[write_p] = I;
write_p = (write_p+1) % Number_of_Words;
filled = filled + 1;
$display("not_full_filled = %d", filled);
end
else
begin
rgf[write_p] = I;
end
end
else if (INST_WRN & !INST_RDN)
begin
if (!empty)
begin
tmp = rgf[read_p];
$display("2_read_p = %d", read_p);
read_p = (read_p +1) % Number_of_Words;
filled = filled -1;
$display("not_empty_filled = %d", filled);
end
end
else ;
if (!filled)
begin
empty = 1;
full = 0;
INST_EMPTYBAR = #DELAY 0 ;
INST_FULLBAR = #DELAY 1 ;
INST_FLAG1BAR = #DELAY 1 ;
INST_FLAG2BAR = #DELAY 1 ;
end
else if (filled == Number_of_Words)
begin
empty = 0;
full = 1;
INST_EMPTYBAR = #DELAY 1 ;
INST_FULLBAR = #DELAY 0 ;
INST_FLAG1BAR = #DELAY 1 ;
INST_FLAG2BAR = #DELAY 1 ;
end
else if ((filled == FLAG1_Location)|(filled == FLAG2_Location))
begin
empty = 0;
full = 0;
if (filled == FLAG1_Location)
begin
INST_EMPTYBAR = #DELAY 1 ;
INST_FULLBAR = #DELAY 1 ;
INST_FLAG1BAR = #DELAY 0 ;
INST_FLAG2BAR = #DELAY 1 ;
end
else // (filled == FLAG2_Location)
begin
INST_EMPTYBAR = #DELAY 1 ;
INST_FULLBAR = #DELAY 1 ;
INST_FLAG1BAR = #DELAY 1 ;
INST_FLAG2BAR = #DELAY 0 ;
end
end
else
begin
empty = 0;
full = 0;
INST_EMPTYBAR = #DELAY 1 ;
INST_FULLBAR = #DELAY 1 ;
INST_FLAG1BAR = #DELAY 1 ;
INST_FLAG2BAR = #DELAY 1 ;
end
end
else // clear is active
begin
empty = 1;
full = 0;
write_p = 0;
read_p = 0;
INST_EMPTYBAR = #DELAY 0 ;
INST_FULLBAR = #DELAY 1 ;
INST_FLAG1BAR = #DELAY 1 ;
INST_FLAG2BAR = #DELAY 1 ;
end
#DELAY O = tmp;
$display("rgf[0] = %b", rgf[0]);
$display("rgf[1] = %b", rgf[1]);
$display("rgf[2] = %b", rgf[2]);
$display("rgf[3] = %b", rgf[3]);
end
end
always @ INST_CP
cp = INST_CP;
endmodule