dpmlt034m.vmd
2.76 KB
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/**************************************************************/
/* Verilog module of datapath cell DPMLT034M */
/* Designed by Lin Yang VLSI Technology Jan. 30, 91 */
/* Designed by Chunling Liu Compass June 30, 92 */
/* Modified by Linda J. Xu Compass Nov. 2 , 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* Y : the input port */
/* Z : the input port */
/* MSB : the output port */
/* LSB : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Number_Of_Columns : the word size of the datapath cell */
/* UNSIGNED : the unsigned boolean/2's complement */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpmlt034m(X, Y, Z, MSB, LSB);
parameter WORDSIZE = 8, Number_Of_Columns = 8, UNSIGNED = 1, DELAY = 30, BF = 1;
input [WORDSIZE-1:0] X, Y, Z;
output [WORDSIZE-1:0] MSB, LSB;
function [2*WORDSIZE-1:0] mlt;
input [WORDSIZE-1:0] x;
input [Number_Of_Columns-1:0] y;
input [WORDSIZE-1:0] z;
reg [WORDSIZE+Number_Of_Columns-1:0] a, b;
reg [WORDSIZE-1:0] sx;
reg [Number_Of_Columns-1:0] sy;
begin
if (UNSIGNED == 0)
begin
if (x[WORDSIZE-1]^y[Number_Of_Columns-1])
begin
if (x[WORDSIZE-1] == 1)
begin
sx = ~x + 1;
sy = y;
end
else if (y[Number_Of_Columns-1] == 1)
begin
sx = x;
sy = ~y + 1;
end
a = ~(sx * sy) + 1;
end
else if (x[WORDSIZE-1]^~ y[Number_Of_Columns-1])
begin
if (x[WORDSIZE-1])
begin
sx = ~x + 1;
sy = ~y + 1;
end
else
begin
sx = x;
sy = y;
end
a = sx * sy;
end
else
a = {WORDSIZE+Number_Of_Columns{1'bx}};
end
else
a = x * y;
if (UNSIGNED == 0)
b = a + {{Number_Of_Columns{z[WORDSIZE-1]}},z};
else
b = a + z;
mlt[WORDSIZE-1:0] = {{WORDSIZE-Number_Of_Columns{1'b0}},b[Number_Of_Columns-1:0]};
mlt[2*WORDSIZE-1:WORDSIZE] = b[WORDSIZE+Number_Of_Columns-1:Number_Of_Columns];
end
endfunction
assign #DELAY {MSB, LSB} = mlt(X,Y,Z);
endmodule