dpmlt035m.vmd
4.31 KB
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/**************************************************************/
/* Verilog module of datapath cell DPMLT035M */
/* Designed by Lin Yang VLSI Technology Jan. 25, 91 */
/* Designed by Chunling Liu Compass July 6, 92 */
/* Modified by Linda J. Xu Compass Nov. 2, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* Y : the input port */
/* Z : the input port */
/* MSB : the output port */
/* LSB : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* CLEAR : the reset signal */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Number_Of_Columns : the word size of the datapath cell */
/* UNSIGNED : the unsigned boolean/2's complement */
/* number_of_pipes : the number of pipeline statge */
/* Cycle_Length : the delay time from input to output */
/**************************************************************/
module dpmlt035m(X, Y, Z, MSB, LSB, INST_CP, CLEAR);
parameter WORDSIZE = 8, Number_Of_Columns = 8,
UNSIGNED = 1,number_of_pipes = 1,
Cycle_Length = 30, BF = 1;
input [WORDSIZE-1:0] X, Y, Z;
output [WORDSIZE-1:0] MSB, LSB;
input INST_CP, CLEAR;
reg [WORDSIZE-1:0] MSB, LSB;
reg [WORDSIZE-1:0] px[1:number_of_pipes];
reg [WORDSIZE-1:0] pz[1:number_of_pipes];
reg [Number_Of_Columns-1:0] py[1:number_of_pipes];
reg [WORDSIZE-1:0] tx[1:number_of_pipes];
reg [Number_Of_Columns-1:0] ty[1:number_of_pipes];
reg [WORDSIZE-1:0] tz[1:number_of_pipes];
reg [WORDSIZE-1:0] ix, sx, iz;
reg [Number_Of_Columns-1:0] iy, sy;
reg [WORDSIZE+Number_Of_Columns-1:0] a, b;
task mlt;
integer n;
begin
// update pipeline registers
for (n=2; n<=number_of_pipes; n=n+1)
begin
tx[n] = tx[n-1];
ty[n] = ty[n-1];
tz[n] = tz[n-1];
end
tx[1] = X;
ty[1] = Y;
tz[1] = Z;
if (UNSIGNED == 0)
begin
ix = tx[number_of_pipes];
iy = ty[number_of_pipes];
iz = tz[number_of_pipes];
if (ix[WORDSIZE-1] ^ iy[Number_Of_Columns-1])
begin
if (ix[WORDSIZE-1] == 1)
begin
sx = ~ix + 1;
sy = iy;
end
else if (iy[Number_Of_Columns-1] == 1)
begin
sx = ix;
sy = ~iy + 1;
end
a = ~(sx * sy) + 1;
end
else if (ix[WORDSIZE-1] ^~ iy[Number_Of_Columns-1])
begin
if (ix[WORDSIZE-1])
begin
sx = ~ix + 1;
sy = ~iy + 1;
end
else
begin
sx = ix;
sy = iy;
end
a = sx * sy;
end
else
a = {WORDSIZE+Number_Of_Columns{1'bx}};
end
else
begin
a = tx[number_of_pipes] * ty[number_of_pipes];
iz = tz[number_of_pipes];
end
if (UNSIGNED == 0)
b = a + {{Number_Of_Columns{iz[WORDSIZE-1]}},iz};
else
b = a + iz;
#Cycle_Length update;
end
endtask
task update;
integer n;
begin
for (n=1; n<=number_of_pipes; n=n+1)
begin
px[n] = tx[n];
py[n] = ty[n];
pz[n] = tz[n];
end
// do the multiplication
LSB = {{WORDSIZE-Number_Of_Columns{1'b0}},b[Number_Of_Columns-1:0]};
MSB = b[WORDSIZE+Number_Of_Columns-1:Number_Of_Columns];
end
endtask
task reset;
integer n;
begin
for (n=1; n<=number_of_pipes; n=n+1)
begin
px[n] = {WORDSIZE{1'b0}};
py[n] = {Number_Of_Columns{1'b0}};
pz[n] = {WORDSIZE{1'b0}};
end
assign LSB = {WORDSIZE{1'b0}};
assign MSB = {WORDSIZE{1'b0}};
end
endtask
always @(posedge CLEAR & INST_CP == 1) reset;
always @(posedge INST_CP) mlt;
endmodule