dpzdt001s.vmd
2.16 KB
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/**************************************************************/
/* Verilog module of datapath cell DPZDT001s */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A : the input port */
/* Control ports */
/* INST_Z : the zero detect flag */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpzdt001s(A, INST_Z);
parameter WORDSIZE = 8, DELAY = 3, BF = 1;
input [WORDSIZE-1:0] A;
output INST_Z;
function zdt;
input [WORDSIZE-1:0] X;
reg [6:0] index;
begin
index = WORDSIZE - 1;
case (|X)
'b1: if (BF == 0)
begin
if ((WORDSIZE == 3)||(WORDSIZE == 4)||((WORDSIZE >= 9)
&&(WORDSIZE <= 14))||((WORDSIZE >= 23)&&(WORDSIZE <= 32))
||((WORDSIZE >= 45)&&(WORDSIZE <= 58)))
zdt = 1'b1;
else zdt = 1'b0;
end
else zdt = 'b 0;
'b0: if (BF == 0)
begin
if ((WORDSIZE == 3)||(WORDSIZE == 4)||((WORDSIZE >= 9)
&&(WORDSIZE <= 14))||((WORDSIZE >= 23)&&(WORDSIZE <= 32))
||((WORDSIZE >= 45)&&(WORDSIZE <= 58)))
zdt = 1'b0;
else zdt = 1'b1;
end
else zdt = 'b 1;
default zdt = 'b x;
endcase
end
endfunction
assign #DELAY INST_Z = zdt(A);
endmodule