module ad01d1 (s, co, a, b, ci);
   input a, b, ci;
   output s, co;
`ifdef SYNTH
    reg co_int, s_int;
    buf b1(co, co_int);
    buf b2(s, s_int);
    always @(a or b or ci)
       {co_int, s_int} = a + b + ci;
`else
   and                  G4(N4, ci, N6);
   or                   G6(N6, a, b);
   and                  G8(N8, N14, N15);
   or                   G9(co, N10, N4);
   and                  G10(N10, a, b);
   or                   G11(N11, N8, ci);
   nand                 G12(N12, N8, ci);
   and                  G13(s, N11, N12);
   or                   G14(N14, a, b);
   nand                 G15(N15, a, b);
`endif
endmodule