module = cs

/* set up a new search path */
search_path = search_path + "../src" + "../../inc" + \
   "../../../lib/verilog/user" + "../../syn"

/* read the verilog sources  and netlists*/

read -f verilog ../src/cs.v
read -f edif csclk.edf
read -f edif csgclk.edf

set_dont_touch csgclk
set_dont_touch csclk

current_design = cs

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

link 

check_design > cs.lint

/* timing/area constraints */
clk_period 		= 16.0

create_clock clk -period clk_period -waveform {0 8.0}
create_clock gclk -period clk_period -waveform {0 8.0}

set_input_delay 3.0 -clock gclk all_inputs()
set_output_delay clk_period - 2.0 all_outputs()

set_load 0.5 all_outputs()
set_driving_cell -cell dfntnb -pin q all_inputs()

set_driving_cell -none {clk gclk}
set_dont_touch_network {clk gclk}
set_drive 0 {clk gclk}
set_arrival 0 {clk gclk}

set_max_fanout 0.02 {reset_l}

/* standard reports & netlist */

include "cs_false_path.tmg"
include "cs.tmg"
include "report.dc"

write -f edif -o cs.edf -hier cs

quit