module = csshuftbl

/* set up a new search path */
search_path = search_path + "../../inc"

/* read the verilog sources */

read -f verilog ../src/csshuftbl.v

current_design = csshuftbl

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

link 

check_design > csshuftbl.lint

/* timing/area constraints */

set_driving_cell -cell jkctnb {shf_state[*]}
set_driving_cell -cell dfntnb {cmd[*]}
set_max_delay 3.0 -to all_outputs()
set_max_transition 0.8 current_design
set_load 0.05 all_outputs()

max_area 200

/* compile */

set_flatten true
set_structure false

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o csshuftbl.edf -hier csshuftbl

quit