cv.ss
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module = cv
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
read -f verilog ../src/cv.v
read -f verilog ../src/cvcompl.v
read -f verilog ../src/cvcompr.v
read -f verilog ../src/cvg.v
read -f verilog ../src/cvmask.v
read -f verilog ../src/cvoffset.v
read -f verilog ../src/cvpipe.v
read -f verilog ../src/cvvalue.v
read -f verilog ../src/cvxcnt.v
current_design = cv
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
/* set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
link
check_design > cv.lint
/* timing/area constraints */
create_clock gclk -period 16.0 -waveform {0.0 8.0}
set_clock_skew -uncertainty 1 gclk
fix_hold gclk
/* inputs */
set_input_delay 2.0 -clock gclk {ew_cv_data[*]}
set_input_delay 2.0 -clock gclk {ew_cv_start_x[*]}
set_input_delay 2.0 -clock gclk {cycle_type}
set_input_delay 2.0 -clock gclk {ew_cv_newspan}
set_input_delay 2.0 -clock gclk {left}
set_max_fanout 0.02 reset_l
/* input drive */
set_driving_cell -cell dfntnb {ew_cv_data[*]}
set_driving_cell -cell dfntnb {ew_cv_start_x[*]}
set_driving_cell -cell dfntnb {cycle_type}
set_driving_cell -cell dfntnb {ew_cv_newspan}
set_driving_cell -cell dfntnb {left}
/* output */
set_output_delay 13.0 -clock gclk all_outputs()
set_load 0.60 {cv_value[*]}
set_load 0.60 {mask15}
set_load 0.60 {x_offset[*]}
set_load 0.60 {y_offset[*]}
set_load 0.60 {x_dither[*]}
set_max_transition 2.0 current_design
max_area 2000
/* compile */
compile -map_effort high -ungroup_all
/* standard reports & netlist */
include "cv.tmg"
include "report.dc"
write -f edif -o cv.edf -hier cv
quit