ew.ss
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module = ew
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 16.0 -waveform {0.0 8.0}; \
set_input_delay 4.0 -clock gclk all_inputs(); \
set_output_delay 2.0 -clock gclk all_outputs(); \
max_delay 3.0 -to all_outputs(); \
set_load 0.2 all_outputs();"
/* read the verilog sources */
read -f edif ewatt.edf
read -f edif ewras.edf
read -f edif ewaddr.edf
read -f verilog ../src/ewctr.v
read -f verilog ../src/ew.v
set_dont_touch ewatt
set_dont_touch ewras
set_dont_touch ewaddr
current_design = ew
link
check_design > ew.lint
set_default_operating_conditions
create_clock gclk -period 16.0 -waveform {0.0 8.0}
set_max_transition 1.5 current_design
/* inputs */
set_input_delay 2.0 -clock gclk all_inputs()
set_input_delay 12.0 -clock gclk {cs_ew_d[*]}
set_input_delay 13.0 -clock gclk {cs_ew_newprim}
set_input_delay 2.0 -clock gclk {left_xminor}
/* driving cells */
set_driving_cell -cell dfntnb all_inputs()
set_driving_cell -none {gclk}
set_drive 0 {gclk}
set_max_fanout 0.02 {reset_l}
set_dont_touch_network {gclk}
set_driving_cell -cell mx21d1 {cs_ew_d[*]}
set_driving_cell -cell mx21d1 {cs_ew_newprim}
/* outputs */
set_output_delay 10.0 -clock gclk all_outputs()
set_output_delay 13.0 -clock gclk {ew_ep_startspan}
set_output_delay 13.0 -clock gclk {ew_ms_length[*]}
set_output_delay 13.0 -clock gclk {ew_ep_d[*]}
set_load 0.08 all_outputs()
set_load 1.70 {ew_ep_startspan}
set_load 0.80 {ew_ms_length[*]}
set_load 0.80 {ew_ep_d[*]}
/* set_dont_use find(cell, "ne35hd130d/*1h") */
include "ew_false.tmg"
compile -map_effort high -ungroup_all
/* register file enable delay less than one half cycle */
set_max_delay 7.5 -to find(pin, "walkatt/regfile/word*/ltch*/e")
set_max_transition 1.5 current_design
/* remove_attribute find(cell, "ewatt") dont_touch
remove_attribute find(cell, "ewras") dont_touch
remove_attribute find(cell, "ewaddr") dont_touch
*/
set_clock_skew -uncertainty 1 gclk
fix_hold gclk
compile -map_effort high -ungroup_all -incremental_mapping
report -reference
report_constraint -all_violators
include "ew.tmg"
include "report.dc"
write -f edif -o ew.edf -hier ew
quit