module = ls
/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
	"create_clock clk -period 16.0 -waveform {0 8.0}; \
	set_input_delay 4.0 -clock clk all_inputs(); \
	set_output_delay 2.0 -clock clk all_outputs(); \
	fix_hold clk; \
	dont_touch_network clk; \
	set_drive 0 {clk}; \
	set_load 1 all_outputs();"

/* setup the search path for includes */
search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib};
search_path = search_path + "../../inc" + "../../syn"

/* read the verilog sources */

read -f verilog ../src/ls.v
read -f edif lsctl.edf
read -f edif lsdp.edf

current_design = ls

set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.00 current_design;

include ls.con

link 

check_design > ls.lint

ungroup -flatten lsctl
ungroup -flatten lsdp

report -reference

report_constraint -all_violators

report_timing -path full -delay max -max_paths 10;

write -f edif -o ls.edf -hier ls
write -f verilog -o ls.vsyn -hier ls

include "ls.tmg"
include "report.dc"

quit