create_clock clock -period 14.0 -waveform { 0.0 7.0 }

set_input_delay 4.0 -clock clk {reset_l}
set_input_delay 4.0 -clock clk {iddq_test}
set_input_delay 5.0 -clock clk {cbus_write_enable}
set_input_delay 5.0 -clock clk {dbus_read_enable}
set_input_delay 5.0 -clock clk {dbus_write_enable}
set_input_delay 5.0 -clock clk {io_load}
set_input_delay 3.0 -clock clk {io_read_select}
set_input_delay 5.0 -clock clk {io_write_select}
set_input_delay 3.0 -clock clk {dma_imem_select}
set_input_delay 5.0 -clock clk {xbus_dmem_select}
set_input_delay 5.0 -clock clk {dma_dm_to_rd}
set_input_delay 5.0 -clock clk {dma_rd_to_dm}
set_input_delay 2.5 -clock clk {dma_address}
set_input_delay 3.0 -clock clk {dma_mask}
set_input_delay 3.0 -clock clk {mem_load}

set_input_delay 3.0 -clock clk {im_to_rd_data}
set_input_delay 8.5 -clock clk {dmem_rd_data}
set_input_delay 3.0 -clock clk {pc}
set_input_delay 3.0 -clock clk {imem_dma_cycle}

set_input_delay 3.0 -clock clk {bist_go}
set_input_delay 3.0 -clock clk {bist_check}

set_input_delay 10.0 -clock clk {cbus_data_in}
set_input_delay 10.0 -clock clk {dbus_data_in}

set_output_delay -max 4.0 -clock clk {cbus_data_out}
set_output_delay -max 4.0 -clock clk {dbus_data_out}

set_output_delay -max 3.0 -clock clk {xbus_data}
set_output_delay -max 11.5 -clock clk {ex_dma_rd_to_dm}
set_output_delay -max 11.5 -clock clk {ex_dma_dm_to_rd}
set_output_delay -max 2.0 -clock clk {mem_write_data}
set_output_delay -max 4.0 -clock clk {imem_datain}
set_output_delay -max 9.5 -clock clk {dma_wen}

set_output_delay -max 7.0 -clock clk {final_pc}
set_output_delay -max 8.5 -clock clk {imem_web}
set_output_delay -max 7.0 -clock clk {imem_csb}
set_output_delay -max 10.8 -clock clk {bist_done}
set_output_delay -max 10.8 -clock clk {bist_fail}
set_output_delay -max 0.5 -clock clk {debug_pc}

set_max_fanout 0.2 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {cbus_write_enable}
set_driving_cell -cell ni01d5 {dbus_read_enable}
set_driving_cell -cell ni01d5 {dbus_write_enable}
set_driving_cell -cell nt01d5 {cbus_data_in, dbus_data_in}

set_load 2.0 {cbus_data_out, dbus_data_out}
set_load 2.0 {xbus_data}
set_load 1.4 {ex_dma_rd_to_dm}
set_load 1.4 {ex_dma_dm_to_rd}
set_load 1.5 {mem_write_data}

set_load 1.5 {imem_datain}
set_load 1.2 {dma_wen}

set_load 1.0 {final_pc}
set_load 1.8 {imem_web}
set_load 2.0 {bist_done}
set_load 0.2 {bist_fail}

set_max_fanout 0.02 {reset_l}

group_path -name non_difficult_group -to all_outputs();
group_path -default -to {final_pc}
group_path -name pc_group -to {final_pc};