rspbusses.ss 5.15 KB
/* setup aliases */
module = rspbusses
wire_load = 256000
standard_load = 0.01
clock = "clk"
default_input_delay = 4.0
default_output_delay = 2.0
default_pin_delay = 11.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 2.0

/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib};

search_path = search_path + "../../inc" + "../../syn"

read -f verilog ../src/rspbusses.v
read -f verilog ../src/ram_bist_imem.v
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
read -f verilog ../../../lib/verilog/user/cbus_driver.v
read -f verilog ../../../lib/verilog/user/dbus_driver.v

current_design = rspbusses_inner

/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top

/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_dont_touch_network clock


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clock }
set_input_delay 0 { clock }
set_fix_hold all_clocks()


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/

set_max_transition default_max_transition current_design
include module + ".con"

/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
link
check_design > module + ".lint"

/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
set_dont_touch cbus_driver
set_dont_touch dbus_driver

ungroup -flatten -all
compile -map_effort high

ungroup -flatten -all
compile -map_effort high

set_clock_skew -uncertainty 1 clk
set_fix_hold all_clocks()
compile -prioritize_min_paths -only_design_rule -incremental_mapping

set_dont_touch cbus_driver false
set_dont_touch dbus_driver false
ungroup -flatten -all

current_design = rspbusses

set_operating_conditions NOM
set_wire_load wire_load -mode top
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock }
set_input_delay 0 { clock }
set_clock_skew -uncertainty 1 clk
set_max_transition default_max_transition current_design
include module + ".con"
include "busses.con"
ungroup -flatten -all

/*****************************************************************************/
/* results                                                                   */
/*****************************************************************************/
report_area
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -path full -delay max -max_paths 50 > "report." + module + ".max_paths"
report_timing -to all_outputs() -nets -max_paths 10 > "report." + module + ".output"
report_timing -from all_inputs() -max_paths 10 >  "report." + module + ".input"

write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module

include "rspbusses.tmg"
include "report.dc"

quit