current_design = rspbusses
reset_design
module = rspbusses
wire_load = 256000
standard_load = 0.01
clock = "clk"
default_input_delay = 2.0
default_output_delay = 2.0
default_pin_delay = 11.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 2.0
default_uncertainty = 1.0

current_design = module

/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top

/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clock }
set_input_delay 0 { clock }
set_fix_hold all_clocks()


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/

set_max_transition 2.0 current_design

set_input_delay 4.0 -clock clock {reset_l}
set_input_delay 4.0 -clock clock {iddq_test}

set_input_delay 5.0 -clock clock {cbus_write_enable}
set_input_delay 5.0 -clock clock {dbus_read_enable}
set_input_delay 5.0 -clock clock {dbus_write_enable}

set_input_delay 5.0 -clock clock {io_load}
set_input_delay 3.0 -clock clock {io_read_select}
set_input_delay 5.0 -clock clock {io_write_select}
set_input_delay 3.0 -clock clock {dma_imem_select}
set_input_delay 5.0 -clock clock {xbus_dmem_select}
set_input_delay 5.0 -clock clock {dma_dm_to_rd}
set_input_delay 5.0 -clock clock {dma_rd_to_dm}
set_input_delay 2.5 -clock clock {dma_address}
set_input_delay 3.0 -clock clock {dma_mask}
set_input_delay 3.0 -clock clock {mem_load}

set_input_delay 3.0 -clock clock {im_to_rd_data}
set_input_delay 8.5 -clock clock {dmem_rd_data}
set_input_delay 3.0 -clock clock {pc}
set_input_delay 3.0 -clock clock {imem_dma_cycle}

set_input_delay 3.0 -clock clock {bist_go}
set_input_delay 3.0 -clock clock {bist_check}

set_input_delay 10.0 -clock clock {cbus_data}
set_input_delay 10.0 -clock clock {dbus_data}

set_output_delay -max 6.0 -clock clock {cbus_data}
set_output_delay -max 6.0 -clock clock {dbus_data}

set_output_delay -max 4.0 -clock clock {xbus_data}
set_output_delay -max 13.5 -clock clock {ex_dma_rd_to_dm}
set_output_delay -max 13.5 -clock clock {ex_dma_dm_to_rd}
set_output_delay -max 3.0 -clock clock {mem_write_data}
set_output_delay -max 4.0 -clock clock {imem_datain}
set_output_delay -max 11.5 -clock clock {dma_wen}

set_output_delay -max 9.0 -clock clock {final_pc}
set_output_delay -max 10.5 -clock clock {imem_web}
set_output_delay -max 9.0 -clock clock {imem_csb}
set_output_delay -max 12.8 -clock clock {bist_done}
set_output_delay -max 12.8 -clock clock {bist_fail}
set_output_delay -max 2.5 -clock clock {debug_pc}

set_max_fanout 0.2 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {xbus_dmem_select}
set_driving_cell -cell ni01d5 {cbus_write_enable}
set_driving_cell -cell ni01d5 {dbus_read_enable} 
set_driving_cell -cell ni01d5 {dbus_write_enable}
set_driving_cell -cell nt01d5 {cbus_data, dbus_data}

set_load 2.0 {cbus_data, dbus_data}
set_load 2.0 {xbus_data}
set_load 1.4 {ex_dma_rd_to_dm}
set_load 1.4 {ex_dma_dm_to_rd}
set_load 1.5 {mem_write_data}

set_load 1.5 {imem_datain}
set_load 1.2 {dma_wen}

set_load 1.0 {final_pc}
set_load 1.8 {imem_web}
set_load 2.0 {bist_done}
set_load 0.2 {bist_fail}

set_max_fanout 0.02 {reset_l}

group_path -name non_difficult_group -to all_outputs()
group_path -default -to {final_pc}
group_path -name pc_group -to {final_pc}