/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "si"
wire_load = 256000
standard_load = 0.01
clock = "clk"
default_input_delay = 1.5
default_output_delay = 13.0
default_pin_delay = 11.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path \
   + "../src" \
   + "../../inc" \
   + "../../../lib/verilog/user" \
   + "../../syn"

/* read the verilog sources */

read -f verilog ../src/si.v
read -f verilog ../src/si_dma.v
read -f verilog ../src/si_control.v
read -f verilog ../src/si_pchclk.v
read -f verilog ../src/si_pif_if.v
read -f verilog ../../../lib/verilog/user/dbus_driver.v
read -f verilog ../../../lib/verilog/user/cbus_driver.v

current_design = module

/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clock }
set_input_delay 0 { clock }

set_max_transition default_max_transition current_design

current_design = si_pif_if
set_dont_touch si_pif_if

set_driving_cell -cell dfntnb pch_reg_msb
set_driving_cell -cell dfntnb pch_cmd_valid
set_driving_cell -cell  pc3d01 pch_rsp_in

current_design = si_pchclk
set_register_type -exact -flip_flop dfntnh { find (cell,"pchclk_reg") }

current_design = si

set_dont_use { ne35hd130d/mbnfnr}
set_dont_use find(cell, "ne35hd130d/*1h")


set_max_fanout 0.02 { reset_l }
set_input_delay 8 -clock clock reset_l

set_dont_touch { ne35hd130d/nt01d* }
set_driving_cell -cell ni01d2 { dbus_enable *_read_enable *_write_enable }
set_input_delay 5.0 -clock clock { cbus_read_enable }
set_input_delay 5.0 -clock clock { cbus_write_enable }
set_input_delay 5.0 -clock clock { dbus_enable }

set_driving_cell -cell nt01d5 { cbus_data dbus_data}
set_load 200 * standard_load { cbus_data dbus_data}
set_input_delay 10.0 -clock clock { cbus_data dbus_data }
set_output_delay 6.0 -clock clock { cbus_data dbus_data }

set_driving_cell -cell ni01d5 { dma_start }
set_load 100 * standard_load { dma_start }
set_max_fanout 2 * standard_load { dma_start }
set_input_delay 3.0 -clock clock { dma_start }

set_input_delay 3.0 -clock clock { dma_grant read_grant }

set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 2 * standard_load { cbus_command cbus_select }

set_load default_pin_load * standard_load { pif_cmd pif_clk }
set_output_delay default_pin_delay -clock clock { pif_cmd pif_clk }


max_area 0

link 

check_design > si.lint

compile -map_effort high -ungroup_all 

include "report.dc"

write -f edif -o si.edf -hier si
write -f db -o si.db -hier si

quit