/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = su
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 70
default_drive_cell = dfntnh
default_drive_pin = q

current_design = module
reset_design

/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top

/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_dont_touch { ne35hd130d/nt01d* }
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_clock_skew -uncertainty 1 clock

set_input_delay default_input_delay -clock clock all_inputs()
set_output_delay default_output_delay -clock clock all_outputs()
set_load default_output_load * standard_load all_outputs()
set_load default_input_load * standard_load all_inputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()

/*****************************************************************************/
/* clock and reset constraints                                               */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock

set_drive 0 reset_l

/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
set_max_transition 2.0 module

set_input_delay 8.0 -clock clock {reset_l};
set_input_delay 3.0 -clock clock {halt};
set_input_delay 3.0 -clock clock {single_step};
set_input_delay 2.5 -clock clock {pc_in_wr_en};
set_input_delay 5.0 -clock clock {pc_data_in[*]};
set_input_delay 5.0 -clock clock {dma_dm_to_rd};
set_input_delay 5.0 -clock clock {dma_rd_to_dm};
set_input_delay 3.0 -clock clock {dma_imem_select};
set_input_delay 1.5 -clock clock {rd_inst};

set_output_delay -max 7.0 -clock clock {chip_sel}; 
set_output_delay -max 2.0 -clock clock {rd_base};
set_output_delay -max 4.0 -clock clock {ls_drive_rd_base};
set_output_delay -max 4.0 -clock clock {rd_offset};
set_output_delay -max 8.0 -clock clock {rd_elem_num};

set_output_delay -max 14.0 -clock clock {su_ex_store};
set_output_delay -max 14.0 -clock clock {su_ex_load};
set_output_delay -max 14.0 -clock clock {vu_ex_store};
set_output_delay -max 14.0 -clock clock {vu_ex_load};
set_output_delay -max 14.0 -clock clock {ex_mfc2};
set_output_delay -max 14.0 -clock clock {ex_mtc2};
set_output_delay -max 14.0 -clock clock {ex_cfc2};
set_output_delay -max 14.0 -clock clock {ex_mfc0};
set_output_delay -max 14.0 -clock clock {ex_su_byte_ls};
set_output_delay -max 14.0 -clock clock {ex_su_half_ls};
set_output_delay -max 14.0 -clock clock {ex_su_uns_ls};
set_output_delay -max 14.0 -clock clock {df_ls_drive_ls_in_wb};
set_output_delay -max 14.0 -clock clock {df_pass_thru}; 

set_output_delay -max 13.0 -clock clock {imem_dma_cycle}; 
remove_output_delay -clock clock {su_nop_debug};
remove_output_delay -clock clock {vu_nop_debug};
set_output_delay -max 13.0 -clock clock {pc};

set_output_delay -max 6.5 -clock clock {branch_or_addr};
set_output_delay -max 4.0 -clock clock {set_broke};
set_output_delay -max 1.0 -clock clock {vu_rd_ld_dec_k};
set_output_delay -max 1.0 -clock clock {vu_rd_st_dec_k};
remove_output_delay -clock clock {break_inst_debug};

/* Ls_data as an SU input really arrives at 12.0 ns. 		*/
/* Synopsys is apparently confused because it is an inout and 	*/
/* adds a 1.4 ns delay on top of that.  We compensate here. 	*/  
set_input_delay 10.6 -clock clk {ls_data};
set_output_delay -max 12.0 -clock clock {ls_data};
 
set_output_delay -max 2.0 -clock clock {vu_comp_k};
set_output_delay -max 6.0 -clock clock {vu_comp};
set_output_delay -max 8.0 -clock clock {vu_func};
set_output_delay -max 8.0 -clock clock {ex_ctc2_vc0};
set_output_delay -max 8.0 -clock clock {ex_ctc2_vc1};
set_output_delay -max 8.0 -clock clock {ex_ctc2_vc2};
set_output_delay -max 1.5 -clock clock {vu_rd_store_type_k};
set_output_delay -max 8.0 -clock clock {vu_elem};

set_output_delay -max 6.0 -clock clock {vu_ld_addr};
set_output_delay -max 6.0 -clock clock {vu_st_addr};
set_output_delay -max 6.0 -clock clock {vu_st_xpose_addr};
set_output_delay -max 6.0 -clock clock {vs}; 
set_output_delay -max 8.0 -clock clock {vt};
set_output_delay -max 3.0 -clock clock {acc_wr_reg}; 
set_output_delay -max 3.0 -clock clock {acc_wr_en};
set_output_delay -max 10.0 -clock clock {store_xpose_rd};
set_output_delay -max 13.0 -clock clock {load_xpose_wb};

set_output_delay -max 1.5 -clock clock {rd_cfvc0_k};
set_output_delay -max 1.5 -clock clock {rd_cfvc1_k};
set_output_delay -max 1.5 -clock clock {rd_cfvc2_k};
 
set_output_delay -max 14.0 -clock clock {cp0_address};
set_output_delay -max 14.0 -clock clock {cp0_write}; 
set_output_delay -max 10.0 -clock clock {cp0_enable}; 
set_output_delay -max 13.0 -clock clock {rd_inst_buf}; 

set_driving_cell -cell ni01d5 -pin z {rd_inst};

set_load .45 {chip_sel};
set_load .35 {rd_base};
set_load .35 {ls_drive_rd_base};
set_load .35 {rd_offset};
set_load .35 {rd_elem_num};
set_load .45 {su_ex_store};
set_load .45 {su_ex_load};
set_load .45 {vu_ex_store};
set_load .45 {vu_ex_load};
set_load .70 {ex_mfc2};
set_load .70 {ex_mtc2};
set_load .45 {ex_cfc2};
set_load 1.7 {ex_mfc0};
set_load .70 {ex_su_byte_ls};
set_load .70 {ex_su_half_ls};
set_load .70 {ex_su_uns_ls};
set_load .45 {df_ls_drive_ls_in_wb};
set_load .70 {df_pass_thru};

set_load .70 {imem_dma_cycle};
set_load 0 su_nop_debug
set_load 0 vu_nop_debug
set_load 1.9 {pc};

set_load .2 {branch_or_addr};
set_load .70 {set_broke};
set_load .35 {vu_rd_ld_dec_k};
set_load .35 {vu_rd_st_dec_k};
set_load 0 break_inst_debug

/* set_load 2.0 {ls_data}; */
set_load 2.3 {vu_comp_k};
set_load 2.3 {vu_comp};
set_load 2.3 {vu_func};
set_load 2.8 {vu_elem};
set_load 2.2 {vs}; 
set_load 1.6 {vt}; 
set_load 1.5 {vu_rd_store_type_k};
set_load 1.8 {rd_cfvc0_k};
set_load 1.8 {rd_cfvc1_k};
set_load 1.8 {rd_cfvc2_k};
set_load 1.9 {ex_ctc2_vc0};
set_load 1.9 {ex_ctc2_vc1};
set_load 1.9 {ex_ctc2_vc2};
set_load 2.0 {acc_wr_reg}; 
set_load 1.2 {acc_wr_en};
set_load 1.4 {vu_ld_addr};
set_load 1.5 {vu_st_addr};
set_load 1.5 {vu_st_xpose_addr};
set_load 1.7 {store_xpose_rd};
set_load 1.2 {load_xpose_wb};

set_load .70 {cp0_address}; 
set_load 1.75 {cp0_write}; 
set_load .40 {cp0_enable}; 

set_load .7 {rd_inst_buf};

group_path -name output_group -to all_outputs();