/* set up a new search path */
search_path = search_path + "../../inc" + "../../syn"

/* read the verilog sources */
read -f verilog ../src/tc.v
read -f edif tc_adj.edf
read -f edif tc_adrs.edf
read -f edif tc_div.edf
read -f edif tc_frac.edf
read -f edif tc_lod.edf
read -f edif tc_sort.edf
read -f edif tc_tilemem.edf

sub_modules = {tc_adj, tc_adrs, tc_div, tc_frac, tc_lod, \
               tc_sort, tc_tilemem}

set_dont_touch sub_modules

current_design = tc

/* set timing constraints */
set_operating_conditions NOM
set_wire_load 256000 -mode top
set_dont_touch { ne35hd130d/nt01d* }

max_area 0

create_clock gclk -period 16.0 -waveform { 0.0 8.0 }
set_clock_skew -uncertainty 1.0 gclk

set_input_delay 2.0 -clock gclk all_inputs()
set_output_delay 13.0 -clock gclk all_outputs()
set_driving_cell -cell dfntnh -pin q all_inputs();
set_max_transition 1.5 current_design
set_load 0.30 { all_inputs() all_outputs() }

set_load 2.0 { all_outputs() }
set_load 2.0 { adrs_bnk0l adrs_bnk1l adrs_bnk2l adrs_bnk3l }
set_load 2.0 { adrs_bnk0h adrs_bnk1h adrs_bnk2h adrs_bnk3h }

set_input_delay 0 gclk
set_drive 0 { gclk }
set_dont_touch_network { gclk }

/* fix s_frac, t_frac grounded outputs */
set_unconnected s_frac_rg[2]
set_unconnected s_frac_rg[1]
set_unconnected s_frac_rg[0]
set_unconnected s_frac_ba[2]
set_unconnected s_frac_ba[1]
set_unconnected s_frac_ba[0]
set_unconnected t_frac_rg[2]
set_unconnected t_frac_rg[1]
set_unconnected t_frac_rg[0]
set_unconnected t_frac_ba[2]
set_unconnected t_frac_ba[1]
set_unconnected t_frac_ba[0]

set_input_delay 12.0 -clock gclk \
   { clr_ind_a[*] clr_ind_b[*]  clr_ind_c[*] clr_ind_d[*] }

set_input_delay 1.4 -clock gclk {s}
set_input_delay 1.4 -clock gclk {t}

link 

check_design > tc.lint

compile
set_dont_touch sub_modules false
compile -ungroup_all -incremental_mapping

module = tc
include "tc.tmg"
include "report.dc"

write -f edif -o tc.edf -hier tc
write -f db -o tc.db

quit