tf.tmg
2.51 KB
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "tf"
clock = "gclk"
default_input_delay = 1.5
default_output_delay = 13.0
default_period = 16.0
default_uncertainty = 1.0
wire_load = 256000
standard_load = 0.01
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
/* loads and drives */
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock }
set_input_delay 0 { clock }
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_input_delay 3.0 -clock clock { tm_aa tm_ab tm_ac tm_ad }
set_input_delay 3.0 -clock clock { tm_ba tm_bb tm_bc tm_bd }
set_input_delay 3.0 -clock clock { tm_ga tm_gb tm_gc tm_gd }
set_input_delay 3.0 -clock clock { tm_ra tm_rb tm_rc tm_rd }
set_input_delay 3.0 -clock clock { lod_frac lge1 }
set_input_delay 5.0 -clock clock { st_span }
set_output_delay 14 -clock clock { tf_a tf_b tf_g tf_r }