top.v
6.43 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
module top;
reg pad_reset_l;
reg test;
reg [14:0] ad16_data_in;
reg ad16_enable_l;
reg ad16_read_l;
reg ad16_write_l;
reg bist_flag;
reg clk;
/**************************************
* clock
*************************************/
initial
begin
clk = 0;
#16 forever
#16 clk = ~clk;
end
/**************************************
* Capture
*************************************/
reg [31:0] fpC_tst;
reg [31:0] fpC_dtst;
reg qsim_test,qsim_dtest;
initial
begin
qsim_test = 0;
qsim_dtest = 0;
if ($test$plusargs("qsim_test")) qsim_test = 1;
if ($test$plusargs("qsim_dtest")) qsim_dtest = 1;
if (qsim_test || qsim_dtest)
begin
if (qsim_test)
begin
fpC_tst = $fopen("tst_test.tab");
$fwrite(fpC_tst,
"clock @C 1(8) 0(8)\n",
"tst_ad16_write_l @O @S 14 "
);
$fdisplay(fpC_tst);
end
else
begin
fpC_tst = $fopen("tst_dtest.tab");
$fwrite(fpC_tst,
"clock @C 1(50) 0(50)\n",
"tst_ad16_write_l @O @S 95 "
);
$fdisplay(fpC_tst);
end
$fwrite(fpC_tst,
"pad_reset_l @I @E 2 \n",
"test @I @E 2 \n",
"st_0 @O @S 14 \n",
"st_1 @O @S 14 \n",
"st_mux @O @S 14 \n",
"ad16_data_in[14:0] @I @E 2 \n",
"ad16_enable_l @I @E 2 \n",
"ad16_read_l @I @E 2 \n",
"ad16_write_l @I @E 2 \n",
"bist_flag @I @E 2 \n",
"tst_ad16_enable_l_0 @O @S 14 \n",
"tst_ad16_enable_l_1 @O @S 14 \n",
"tst_ad16_read_l @O @S 14 \n",
"tst_by_pass @O @S 14 \n",
"tst_bist_mode @O @S 14 \n",
"tst_iost_mode @O @S 14 \n",
"tst_rac_reset @O @S 14 \n",
"tst_ext_be @O @S 14 \n",
"tst_c_ctl_en @O @S 14 \n",
"tst_c_ctl_i[5:0] @O @S 14 \n",
"tst_c_ctl_ld @O @S 14 \n",
"tst_synclk_set @O @S 14 \n",
"tst_pwr_up @O @S 14 \n",
"tst_idd_test @O @S 14 \n",
"tst_reset_l_0 @O @S 14 \n",
"tst_reset_l_1 @O @S 14 \n",
"tst_reset_l_2 @O @S 14 \n",
"tst_reset_l_3 @O @S 14 \n",
"tst_reset_l_4 @O @S 14 \n",
"tst_reset_l_5 @O @S 14 \n",
"tst_reset_l_6 @O @S 14 \n",
"tst_reset_l_7 @O @S 14 \n",
"tst_reset_l_8 @O @S 14 \n",
"tst_reset_l_9 @O @S 14 \n"
);
$fdisplay(fpC_tst);
@(posedge clk);
forever
begin
@(negedge clk);
#4;
$fwrite(fpC_tst,
"%b ", U0.tst_ad16_write_l ,
"%b ", U0.pad_reset_l ,
"%b ", U0.test ,
" %b ", U0.st_0 ,
"%b ", U0.st_1 ,
"%b ", U0.st_mux ,
" 0x%h ", U0.ad16_data_in[14:0] ,
"%b ", U0.ad16_enable_l ,
"%b ", U0.ad16_read_l ,
"%b ", U0.ad16_write_l ,
"%b ", U0.bist_flag ,
"%b ", U0.tst_ad16_enable_l_0 ,
"%b ", U0.tst_ad16_enable_l_1 ,
"%b ", U0.tst_ad16_read_l ,
"%b ", U0.tst_by_pass ,
"%b ", U0.tst_bist_mode ,
"%b ", U0.tst_iost_mode ,
"%b ", U0.tst_rac_reset ,
"%b ", U0.tst_ext_be ,
"%b ", U0.tst_c_ctl_en ,
"0x%h ", U0.tst_c_ctl_i[5:0] ,
"%b ", U0.tst_c_ctl_ld ,
"%b ", U0.tst_synclk_set ,
"%b ", U0.tst_pwr_up ,
"%b ", U0.tst_idd_test ,
"%b ", U0.tst_reset_l_0 ,
"%b ", U0.tst_reset_l_1 ,
"%b ", U0.tst_reset_l_2 ,
"%b ", U0.tst_reset_l_3 ,
"%b ", U0.tst_reset_l_4 ,
"%b ", U0.tst_reset_l_5 ,
"%b ", U0.tst_reset_l_6 ,
"%b ", U0.tst_reset_l_7 ,
"%b ", U0.tst_reset_l_8 ,
"%b ", U0.tst_reset_l_9
);
$fdisplay(fpC_tst);
end
end
end
/**************************************
* Stimulus
*************************************/
initial
begin
pad_reset_l = 'hx;
test='hx;
ad16_data_in = 'hx;
ad16_enable_l = 'hx;
ad16_read_l = 'hx;
ad16_write_l = 'hx;
bist_flag = 'hx;
repeat (1) @(posedge clk);
if (qsim_test)
begin
`include "test.diag"
end
else
if (qsim_dtest)
begin
`include "delay.diag"
end
#4; reset; repeat (8) @(posedge clk);
$finish;
end
/**************************************
* DUT
*************************************/
tst U0(
.clock(clk),
.pad_reset_l(pad_reset_l),
.test(test),
.ad16_data_in(ad16_data_in),
.ad16_enable_l(ad16_enable_l),
.ad16_read_l(ad16_read_l),
.ad16_write_l(ad16_write_l),
.bist_flag(bist_flag)
);
wire [1:0] st = {U0.st_1,U0.st_0};
/**************************************
* tasks
*************************************/
//////////
task reset;
begin
pad_reset_l = 0; @(posedge clk);
pad_reset_l = 0; test = 0; repeat (4) @(posedge clk);
end
endtask
//////////
task next_state;
begin
pad_reset_l = 1; test = 1; @(posedge clk);
#4 pad_reset_l = 0; @(posedge clk);
end
endtask
/**************************************
* dump
*************************************/
initial $dumpvars(0,top);
endmodule