#!/usr/bin/perl

$module = $ARGV[0];

open(DC, "> edf2vsyn.$module");

printf DC "read -f edif $module.edf \n";
printf DC "current_design = $module \n";
printf DC "link \n";
printf DC "write -f verilog -o $module.vsyn -hier $module \n";
printf DC "quit \n";
close(DC);

system "dc_shell -f edf2vsyn.$module";
system "rm edf2vsyn.$module";