divctl.cmd
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# constraint file
# global constraints
#
set process slow
set temperature 125
set vddlevel 2.7
set maxrampdelay 2.0
# block specific constraints
#
set frozen div_clkgen
#
set frequency 62.5 CLK
#
set setup 6.0 Reset_l --> CLK
set setup 6.0 OpCode[*] --> CLK
set setup 6.0 OpCodeValid --> CLK
set setup 3.0 VTL[*] --> CLK
set setup 3.0 VTH[*] --> CLK
set setup 6.0 El2 --> CLK
set setup 3.0 ROMData[*] --> CLK
#
set outdelay 11.0 CLK --> RADDR[*]
set outdelay 8.0 CLK --> DivOut[*]
#
set inputdelay 8.0 Reset_l
set inputdelay 8.0 OpCode[*]
set inputdelay 8.0 OpCodeValid
set inputdelay 12.0 VTH[*]
set inputdelay 12.0 VTL[*]
set inputdelay 8.0 El2
set inputdelay 12.0 ROMData[*]
#
#
# input drive strengts
#
set drive 0 CLK
#
# output loading
#
set load 0.5 RADDR[*]
set load 1.0 DivOut[*]
show environment