module = vu
/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"

alias set_default_timing_constraints \
	"create_clock clk -period 16.0 -waveform {0 8.0}; \
	set_clock_skew -uncertainty 1 clk; \
	set_input_delay 15.0 -clock clk all_inputs(); \
	set_output_delay -max 14.5 -clock clk all_outputs(); \
	set_driving_cell -none  {clk}; \
	set_driving_cell -cell in01d3  all_inputs(); \
	set_drive 0 {clk}; \
	set_load 1.0 all_outputs();"

/* setup the search path for includes */
search_path = search_path + "../src" + "../../syn"

/* read the verilog sources */

read -f verilog ../src/vu.v
read -f edif vusl.edf
read -f edif vurfctl.edf
read -f edif div.edf

current_design = vu

set_default_operating_conditions
set_default_timing_constraints

set_max_transition 2.0 current_design;

set_disable_timing su_data_to_from

include vu.con

link 

current_design = vu

check_design > vu.lint

report -reference > report/vu.ref

report_area > report/vu.area

report_net > report/vu.net


report_constraint -all_violators > report/vu.violators


report_timing -path full -delay max -max_paths 10 > report/vu.full.paths

write -f edif -o vu.edf -hier vu


include "vu.tmg"
include "report.dc"


quit