current_design = vu
reset_design 

/* set default operating conditions */
set_operating_conditions NOM -library rcp.db;
set_wire_load 256000 -mode top;

/* set_default_timing_constraints */
create_clock clk -period 16.0 -waveform {0 8.0};
set_clock_skew -uncertainty 1 clk;
set_input_delay 15.0 -clock clk all_inputs();
set_output_delay -max 14.5 -clock clk all_outputs();
set_driving_cell -none  {clk};
set_driving_cell -cell in01d0  all_inputs();
set_drive 0 {clk};
set_load 1.0 all_outputs();


set_max_transition 2.0 current_design;

set_disable_timing su_data_to_from
set_input_delay 8 -clock clk {reset_l};

set_input_delay 12 -clock clk {su_instvld_rd};
set_input_delay 14 -clock clk {su_instvldk_rd};
set_input_delay 14.5 -clock clk {su_storeinst_rd};
set_input_delay 10 -clock clk {su_vseqone_rd};
set_input_delay 8 -clock clk {su_instelem_rd};
set_input_delay 8 -clock clk {su_instfunc_rd};
set_input_delay 14.5 -clock clk {su_rdcmpcd_rd};
set_input_delay 14.5 -clock clk {su_rdcryout_rd};
set_input_delay 14.5 -clock clk {su_rdcmpcdad_rd};
set_input_delay 8 -clock clk {su_wrcmpcd_wb};
set_input_delay 8 -clock clk {su_wrcryout_wb};
set_input_delay 8 -clock clk {su_wrcmpcdad_wb};


set_input_delay 10 -clock clk {su_st_rnum_rd};
set_input_delay 10 -clock clk {su_xp_rnum_rd};
set_input_delay 14 -clock clk {su_ld_rnum_ac};
set_input_delay 10 -clock clk {su_vs_addr_rd};
set_input_delay 8  -clock clk  {su_vt_addr_rd};
set_input_delay 14 -clock clk  {su_vd_addr_ac};

set_input_delay 14 -clock clk {su_wbv_wr_en_ac};
set_input_delay 14 -clock clk {su_bwe_ac};
set_input_delay 10 -clock clk {su_st_xposeop_rd};
set_input_delay 3  -clock clk {su_ld_xposeop_wb};

set_input_delay 12 -clock clk {su_data_to_from};
set_output_delay -max 12.0 -clock clk {su_data_to_from};