dont_touch_network su_vt_addr_rd;

set_driving_cell -cell in01d2	vdp_achizero0_wb;
set_driving_cell -cell in01d2	vdp_achizero1_wb;
set_driving_cell -cell in01d2	vdp_achione0_wb;
set_driving_cell -cell in01d2	vdp_achione1_wb;
set_driving_cell -cell in01d2	vdp_vt_sign0_mu;
set_driving_cell -cell in01d2	vdp_vt_sign1_mu;
set_driving_cell -cell in01d5	su_vt_addr_rd;

set_dont_touch vuctlsl0
set_dont_touch vuctlsl1

set_dont_touch regfile_decode
set_dont_touch buffer_ninv
set_dont_touch buffer_inv

set_dont_touch xp_address_buf0
set_dont_touch xp_address_buf1
set_dont_touch xp_address_buf2
set_dont_touch xp_address_buf3
set_dont_touch xp_address_buf4

set_dont_touch st_address_buf0
set_dont_touch st_address_buf1
set_dont_touch st_address_buf2
set_dont_touch st_address_buf3
set_dont_touch st_address_buf4

set_dont_touch ld_address_buf0
set_dont_touch ld_address_buf1
set_dont_touch ld_address_buf2
set_dont_touch ld_address_buf3
set_dont_touch ld_address_buf4

set_dont_touch vctcontbus0nt
set_dont_touch vctcontbus1nt
set_dont_touch vctcontbus2nt
set_dont_touch vctcontbus3nt

set_dont_touch vctcontbusmx0mu
set_dont_touch vctcontbusmx1mu
set_dont_touch vctcontbusmx2mu
set_dont_touch vctcontbusmx3mu

set_dont_touch vctcontbusin0mu
set_dont_touch vctcontbusin1mu


set_input_delay 8 -clock clk {reset_l};

set_max_fanout 0.02 {reset_l};

set_input_delay 12 -clock clk {su_instvld_rd};
set_input_delay 13 -clock clk {su_storeinst_rd};
set_input_delay 13 -clock clk {su_storecfc2_rd};
set_input_delay 10 -clock clk {su_vseqone_rd};
set_input_delay 8 -clock clk {su_instelem_rd};
set_input_delay 8 -clock clk {su_instfunc_rd};
set_input_delay 13 -clock clk {su_rdcmpcd_rd};
set_input_delay 13 -clock clk {su_rdcryout_rd};
set_input_delay 13 -clock clk {su_rdcmpcdad_rd};
set_input_delay 8 -clock clk {su_wrcmpcd_wb};
set_input_delay 8 -clock clk {su_wrcryout_wb};
set_input_delay 8 -clock clk {su_wrcmpcdad_wb};

set_input_delay 8 -clock clk {vdp_vs_zero0_mu, vdp_vs_zero1_mu};
set_input_delay 8 -clock clk {vdp_vt_zero0_mu, vdp_vt_zero1_mu};
set_input_delay 12 -clock clk {vdp_vs_sign0_rd, vdp_vs_sign1_rd};
set_input_delay 2.5 -clock clk {vdp_vt_sign0_mu, vdp_vt_sign1_mu};
set_input_delay 10 -clock clk {vdp_aluovr0_mu, vdp_aluovr1_mu};
set_input_delay 10 -clock clk {vdp_aluco0_mu, vdp_aluco1_mu};
set_input_delay 11.5 -clock clk {vdp_aluzero0_mu, vdp_aluzero1_mu};
set_input_delay 11.5 -clock clk {vdp_aluone0_mu, vdp_aluone1_mu};

set_input_delay 8 -clock clk {vdp_addlwco0_ac, vdp_addlwco1_ac};
set_input_delay 8 -clock clk {vdp_addlwov0_ac, vdp_addlwov1_ac};
set_input_delay 8 -clock clk {vdp_csupco0_ac, vdp_csupco1_ac};
set_input_delay 12 -clock clk {vdp_addupco0_ac, vdp_addupco1_ac};

set_input_delay 4 -clock clk {vmu_co_clal0_ac, vmu_co_clal1_ac};
set_input_delay 4 -clock clk {vmu_co_clah0_ac, vmu_co_clah1_ac};

set_input_delay 2 -clock clk {vdp_acc0bit15_wb, vdp_acc0bit21_wb};
set_input_delay 2 -clock clk {vdp_acc0bit31_wb, vdp_acc0bit47_wb};

set_input_delay 3 -clock clk {vdp_achizero0_wb, vdp_achione0_wb, vdp_acmizero0_wb};

set_input_delay 2 -clock clk {vdp_acc1bit15_wb, vdp_acc1bit21_wb};
set_input_delay 2 -clock clk {vdp_acc1bit31_wb, vdp_acc1bit47_wb};

set_input_delay 3 -clock clk {vdp_achizero1_wb, vdp_achione1_wb, vdp_acmizero1_wb};



set_output_delay -max 1.0 -clock clk {vct_regopssl_rd};

set_output_delay -max 3.3 -clock clk {vct_qurtlosl_rd, vct_qurthisl_rd};
set_output_delay -max 2.5 -clock clk {vct_halflosl_rd, vct_halfhisl_rd};
set_output_delay -max 1.5 -clock clk {vct_whllosl_rd, vct_whlhisl_rd};

set_output_delay -max 2.0 -clock clk {vct_couprsl_mu, vct_smuprsl_mu, vct_colwrsl_mu};

set_output_delay -max 2.0 -clock clk {vct_smlwrsl0_mu, vct_smlwrsl1_mu};

set_output_delay -max 12.0 -clock clk {vct_sgnmplr_mu, vct_sgnmplcnd_mu, vct_shftlftone_mu};

set_output_delay -max 10.5 -clock clk {vct_aluctl0_mu, vct_aluctl1_mu};
set_output_delay -max 10.5 -clock clk {vct_alucin0_mu, vct_alucin1_mu};
set_output_delay -max 6.0 -clock clk {vct_compvt0_mu, vct_compvt1_mu};

set_output_delay -max 3.0 -clock clk	{vct_aclwsl0_ac, vct_aclwsl1_ac};
set_output_delay -max 12.0 -clock clk {vct_cslwcsl_ac};

set_output_delay -max 9.0 -clock clk {vct_csupcen0_ac, vct_csupcen1_ac};

set_output_delay -max 2.0 -clock clk	{vct_acmisl0_ac, vct_acmisl1_ac};
set_output_delay -max 1.0 -clock clk	{vct_acupsl0_ac, vct_acupsl1_ac};

set_output_delay -max 8.0 -clock clk {vct_rndvlu0_ac, vct_rndvlu1_ac};
set_output_delay -max 10.0 -clock clk {vct_cslwasl0_ac, vct_cslwasl1_ac};
set_output_delay -max 10.0 -clock clk {vct_cslwbsl0_ac, vct_cslwbsl1_ac};
set_output_delay -max 9.0 -clock clk {vct_addlwci0_ac, vct_addlwci1_ac};
set_output_delay -max 9.0 -clock clk {vct_csupasl0_ac, vct_csupasl1_ac};
set_output_delay -max 9.0 -clock clk {vct_csupbsl0_ac, vct_csupbsl1_ac};
set_output_delay -max 9.0 -clock clk {vct_incrdwn0_ac, vct_incrdwn1_ac};
set_output_delay -max 9.0 -clock clk {vct_incrci0_ac, vct_incrci1_ac};
set_output_delay -max 7.0 -clock clk {vct_incrmxsl0_ac, vct_incrmxsl1_ac};

set_output_delay -max 7.0 -clock clk	{vct_rsltsl0_wb, vct_rsltsl1_wb};
set_output_delay -max 7.0 -clock clk	{vct_clprslt0_wb, vct_clprslt1_wb};

set_output_delay -max 2.0 -clock clk	{su_storeinst_mu, su_storecfc2_mu};

set_input_delay 12.0 -clock clk {su_cont_to_from};
set_output_delay -max 12.0 -clock clk {su_cont_to_from};


set_input_delay 8.3 -clock clk {su_xp_rnum_rd[0]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[1]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[2]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[3]};
set_input_delay 8 -clock clk {su_xp_rnum_rd[4]};

set_input_delay 8.5 -clock clk {su_st_rnum_rd[0]};
set_input_delay 8.5 -clock clk {su_st_rnum_rd[1]};
set_input_delay 8.5 -clock clk {su_st_rnum_rd[2]};
set_input_delay 8.5 -clock clk {su_st_rnum_rd[3]};
set_input_delay 8.5 -clock clk {su_st_rnum_rd[4]};

set_input_delay 11 -clock clk {su_ld_rnum_ac[0]};
set_input_delay 11 -clock clk {su_ld_rnum_ac[1]};
set_input_delay 11 -clock clk {su_ld_rnum_ac[2]};
set_input_delay 11 -clock clk {su_ld_rnum_ac[3]};
set_input_delay 11 -clock clk {su_ld_rnum_ac[4]};

set_input_delay 7 -clock clk {su_vs_addr_rd};
set_input_delay 8 -clock clk {su_vt_addr_rd};
set_input_delay 13.0 -clock clk {su_vd_addr_ac};
set_input_delay 13.0 -clock clk {su_wbv_wr_en_ac};
set_input_delay 13.0 -clock clk {su_bwe_ac};
set_input_delay 8 -clock clk {su_xposeop_rdac};
set_drive 0 {vct_slice0};
set_input_delay 0.0 -clock clk {vct_slice0};
set_drive 0 {vct_slice1};
set_input_delay 0.0 -clock clk {vct_slice1};

set_output_delay -max 5 -clock clk {vct_rfadrt_hi0_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_hi0_wb}
set_output_delay -max 5 -clock clk {vct_rfadrt_lo0_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_lo0_wb}
set_output_delay -max 2 -clock clk {vct_rfadrt_st0_rd}
set_output_delay -max 2 -clock clk {vct_rfadrf_st0_rd}
set_output_delay -max 3 -clock clk {vct_rfadrt_vs0_rd}
set_output_delay -max 3 -clock clk {vct_rfadrf_vs0_rd}
set_output_delay -max 7 -clock clk {vct_rfadrt_vt0_rd}
set_output_delay -max 7 -clock clk {vct_rfadrf_vt0_rd}
set_output_delay -max 5 -clock clk {vct_rfadrt_vd0_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_vd0_wb}

set_output_delay -max 5 -clock clk {vct_rfadrt_hi1_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_hi1_wb}
set_output_delay -max 5 -clock clk {vct_rfadrt_lo1_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_lo1_wb}
set_output_delay -max 2 -clock clk {vct_rfadrt_st1_rd}
set_output_delay -max 2 -clock clk {vct_rfadrf_st1_rd}
set_output_delay -max 3.5 -clock clk {vct_rfadrt_vs1_rd}
set_output_delay -max 3.5 -clock clk {vct_rfadrf_vs1_rd}
set_output_delay -max 7 -clock clk {vct_rfadrt_vt1_rd}
set_output_delay -max 7 -clock clk {vct_rfadrf_vt1_rd}
set_output_delay -max 5 -clock clk {vct_rfadrt_vd1_wb}
set_output_delay -max 5 -clock clk {vct_rfadrf_vd1_wb}