current_design = vurfctl

set_load 2.0 {su_sclrdatasl_rd};
set_load 4.0 {su_qrtdatasl_rd};
set_load 2.5 {su_hlfdatasl_rd};
set_load 1.75 {su_whldatasl_rd};
set_load 1.5 {su_vd_addr_wb};
set_load 1.5 {su_ld_rnum_wb};
set_load 1.0 {vct_wbv_wr_en_wb};
set_load 1.0 {su_bwe_wb};

set_input_delay 4 -clock clk {reset_l};
set_input_delay 8 -clock clk {su_instelem_rd};
set_input_delay 14.0 -clock clk {su_bwe_ac};
set_input_delay 14.0 -clock clk {su_vd_addr_ac};
set_input_delay 14.0 -clock clk {su_ld_rnum_ac};
set_input_delay 8 -clock clk {su_xposeop_rdac};
set_input_delay 13.5 -clock clk {vct_instvld_ac};
set_input_delay 14.0 -clock clk {su_wbv_wr_en_ac};
set_input_delay 14.0 -clock clk {vct_dvtypop_ac};
set_input_delay 14.0 -clock clk {vct_vs_addr_ac};


set_output_delay -max 5 -clock clk {su_sclrdatasl_rd};
set_output_delay -max 5 -clock clk {su_qrtdatasl_rd};
set_output_delay -max 5 -clock clk {su_hlfdatasl_rd};
set_output_delay -max 4 -clock clk {su_whldatasl_rd};

set_output_delay -max 13 -clock clk {su_vd_addr_wb};
set_output_delay -max 13 -clock clk {su_ld_rnum_wb};

set_output_delay -max 11.5 -clock clk {vct_wbv_wr_en_wb};
set_output_delay -max 13 -clock clk {su_bwe_wb};