#!/bin/csh -f
#
#  Shell script for generating tabular trace file 
#
#  Usage: do_sim <test>
#
#  12/2/94   TD
#

if ( $#argv != 1 ) then
  echo "Usage: $0 <test>"
  exit
endif

vlsishell << EOF
set echo on

####################################
# invoke qsim and load netlist
####################################
qsim
mode compassqsim
load [nls]cs

####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
trace (static, tabular)
#options tabularReportOnChange
#trace (dynamic, tabular)

####################################
# display current environment
####################################
preprocess
simparms
options
trace
modeloptions

####################################
# bus and signal aliases
####################################
vector xbus_cs_data[63:0]   
vector texel_size[1:0]     
vector w_addr_in[5:0] clklogic.w_addr_in_reg_5_.q clklogic.w_addr_in_reg_4_.q clklogic.w_addr_in_reg_3_.q clklogic.w_addr_in_reg_2_.q clklogic.w_addr_in_reg_1_.q clklogic.w_addr_in_reg_0_.q
vector read_adrs[5:0]    
vector gclklogic.shf_state[4:0]   
vector shf_state[4:0] gclklogic.shf_state[4:0]
vector tile_addr[2:0]  
vector cs_tc_data[47:0]     
vector cs_ew_data[63:0]    
vector cmd[5:0]           
equiv gclklogic.decode.sync_tile_state sync_tile_state
equiv gclklogic.decode.sync_pipe_state sync_pipe_state
equiv gclklogic.decode.sync_full_state sync_full_state
equiv gclklogic.decode.sync_load_state_reg.q sync_load_state

####################################
# assign static inputs
####################################

####################################
# list signals to be dumped in trace file
####################################
# inputs
#watch xbus_cs_data
#watch xbus_cs_valid
#watch ew_cs_busy
#watch ms_busy
#watch rel_sync_tile
#watch rel_sync_pipe
#watch rel_sync_full
#watch rel_sync_load
#watch texel_size
#watch copy_fill
#watch reset_l
#watch gclk
#watch clk
# outputs
#watch tile_addr
#watch cs_tc_data
#watch we_tile_size
#watch we_tile_attr
#watch cs_ew_data
#watch cs_ew_newprim
#watch cs_xbus_req
#watch cmd
#watch start_prim
#watch attr_valid
#watch cmd_busy
## registers
#
#vector gclklogic.fiforead.read_adrs[5:0]
#watch gclklogic.fiforead.read_adrs
#
#vector gclklogic.decode.cmd[5:0]
#watch gclklogic.decode.cmd
#vector gclklogic.decode.cmd_size[4:0]
#watch gclklogic.decode.cmd_size
#watch gclklogic.decode.start_prim
#vector gclklogic.decode.delay_state[4:0]
#watch gclklogic.decode.delay_state
#vector gclklogic.decode.fifo_data[63:0]
#watch gclklogic.decode.fifo_data
#watch gclklogic.decode.attr_valid
#watch gclklogic.decode.stop_wen
#watch gclklogic.decode.sync_tile_state
#watch gclklogic.decode.sync_pipe_state
#watch gclklogic.decode.sync_full_state
#watch sync_load_state
#
#vector gclklogic.shuffle.shf_state[4:0]
#watch gclklogic.shuffle.shf_state
#
##io_buf debug
#watch msbbuf.wen
#watch msbbuf.clk
#vector msbbuf.ra[4:0]
#watch msbbuf.ra
#vector msbbuf.wa[4:0]
#watch msbbuf.wa
#vector msbbuf.di[31:0]
#watch msbbuf.di
#vector msbbuf.dout[31:0]
#watch msbbuf.dout
#
#watch lsbbuf.wen
#watch lsbbuf.clk
#vector lsbbuf.ra[4:0]
#watch lsbbuf.ra
#vector lsbbuf.wa[4:0]
#watch lsbbuf.wa
#vector lsbbuf.di[31:0]
#watch lsbbuf.di
#vector lsbbuf.dout[31:0]
#watch lsbbuf.dout
#
#
#vector gclklogic.shuffle.off_addr[4:0]
#watch gclklogic.shuffle.off_addr
#vector gclklogic.shuffle.shf_state[4:0]
#watch gclklogic.shuffle.shf_state
#vector gclklogic.shuffle.base_addr[4:0]
#watch gclklogic.shuffle.base_addr
#
#watch gclklogic.shuffle.inc_shf_state
#watch gclklogic.shuffle.update_shf
#
#watch gclklogic.decode.state_zero
#vector gclklogic.decode.words_fifo[5:0]
#watch gclklogic.decode.words_fifo
#vector gclklogic.decode.size_prim[4:0]
#watch gclklogic.decode.size_prim
#watch gclklogic.decode.one_word_cmd
#watch gclklogic.decode.ew_busy
#watch gclklogic.decode.ms_busy
#watch gclklogic.decode.empty
#watch gclklogic.decode.sync_none
#watch gclklogic.decode.sync_tile_state
#watch gclklogic.decode.sync_pipe_state
#watch gclklogic.decode.sync_full_state
#watch gclklogic.decode.sync_load_state_reg.q
#
##
#vector gclklogic.fiforead.read_adrs[5:0]
#watch gclklogic.fiforead.read_adrs
#watch gclklogic.fiforead.gclk
#watch gclklogic.fiforead.reset_l
#
##
#watch gclklogic.fiforead.read_adrs_reg_reg_5_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_5_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_5_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_5_.q
#
#watch gclklogic.fiforead.read_adrs_reg_reg_4_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_4_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_4_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_4_.q
#
#watch gclklogic.fiforead.read_adrs_reg_reg_3_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_3_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_3_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_3_.q
#
#watch gclklogic.fiforead.read_adrs_reg_reg_2_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_2_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_2_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_2_.q
#
#watch gclklogic.fiforead.read_adrs_reg_reg_1_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_1_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_1_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_1_.q
#
#watch gclklogic.fiforead.read_adrs_reg_reg_0_.d
#watch gclklogic.fiforead.read_adrs_reg_reg_0_.cp
#watch gclklogic.fiforead.read_adrs_reg_reg_0_.cdn
#watch gclklogic.fiforead.read_adrs_reg_reg_0_.q
#
##
#vector clklogic.wr_adrs[4:0]
#watch clklogic.wr_adrs
#
####################################
# open trc file
####################################
output (only) [trc]$1

####################################
# load sim file
####################################
load [sim]$1

####################################
# close trc file
####################################
output .

####################################
# display % of nodes toggled
####################################
toggles (totals)

q
q
EOF