test.1 1.57 KB
####################################################
#  this file produced by tab2sim                   #
#                                                  #
#  tab2sim written by Rob Moore                    #
#  Silicon Graphics, Inc.                          #
#  November  1994                                  #
####################################################

alias i inputs
alias c charged
alias t test

forced high vdd
forced low vss

echo #
echo #  Test all signal types, tab2sim
echo #
clock gclk 0(8.00) 1(8.00) 
echo #original sim at cycle :0 absolute time:0.00
s 1.00
l sig_e
s 16.00
h sig_e
s 16.00
l sig_e
s 2.00
i 'h11 sig_d
s 14.00
h sig_e
s 1.00
h sig_a
s 2.00
i 'haaa sig_b
s 15.00
i 'h22 sig_d
s 1.00
i 'h555 sig_b
s 16.00
i 'haaa sig_b
s 13.00
l sig_e
s 1.00
l sig_a
s 1.00
i 'h33 sig_d
s 1.00
i 'h555 sig_b
s 13.00
h sig_e
s 3.00
i 'haaa sig_b
s 14.00
h sig_a
s 1.00
i 'h44 sig_d
s 1.00
i 'h555 sig_b
s 16.00
i 'haaa sig_b
s 13.00
l sig_e
s 2.00
i 'h55 sig_d
s 1.00
i 'h555 sig_b
s 13.00
h sig_e
s 1.00
l sig_a
s 2.00
i 'haaa sig_b
s 15.00
i 'h66 sig_d
s 1.00
c * sig_b
s 14.00
h sig_a
s 2.00
i 'haaa sig_b
s 15.00
i 'h77 sig_d
s 1.00
i 'h555 sig_b
s 14.00
l sig_a
s 2.00
i 'haaa sig_b
s 31.00
c * sig_d
s 16.00
c * sig_d
s 16.00
c * sig_d
s 13.00
echo #original sim at cycle :20 absolute time:320.00
s 3.00
i 'h77 sig_d
s 317.00
echo #original sim at cycle :40 absolute time:640.00
s 320.00
echo #original sim at cycle :60 absolute time:960.00
s 320.00
echo #original sim at cycle :80 absolute time:1280.00
s 320.00
echo #original sim at cycle :100 absolute time:1600.00
s 0.00