#!smake
#
#  This makefile has rules for making both the executables
#  which make up the simulator, and for running test cases.
#
# $Revision: 1.1.1.1 $
#
COMMONPREF=cs
PRDEPTH = ../../..
include $(PRDEPTH)/PRdefs

#
#  Directories
#
SIMLIB		= ../../simlib
SRC    		= ../../src
HDR    		= ../../hdr
WIR    		= Wir
INDATA 		= InData
OUTDATA		= OutData

SUBDIRS		= $(WIR)

#
#		Look in $(SRC) directory for C-sim source
#
.PATH:		$(SRC)

#
#  C Sources
#
TEST_FILES 	= \
        	$(SRC)/csclk.c \
        	$(SRC)/csgclk.c \
		bits_gram.c \
		expand.c \
        	driver.c \
        	cs_test_0.c

#
#  Object Files
#
TEST_OBJ 	= $(TEST_FILES:.c=.o)
TEST_OBJS    	= $(TEST_OBJ:T)

#
#  Header file Directories
#
LCINCS 		= -I. \
	 	-I$(PRDEPTH)/include \
	 	-I$(SIMLIB) \
	 	-I$(HDR)

GCINCS 		=

#
# Compiler options
#
OPTIMIZER	= -g
LCOPTS		= -fullwarn

#
#  Linker Directories and Options
# 
LLDOPTS 	= -L. -L$(SIMLIB)
GLDOPTS 	=
LLDLIBS 	= -lsimlib

#
#  Verilog compiler options
#
LVCSOPTS = +incdir+$(PRDEPTH)/hw/chip/rcp/inc

RTLOPTS  = -y $(PRDEPTH)/hw/chip/rcp/cs/src               	\
	   -y $(PRDEPTH)/hw/chip/lib/verilog/stdcell		\
	   -y $(PRDEPTH)/hw/chip/lib/verilog/ram                \
	    +libext+.v						\
	    -Mdir=rtlcsrc

SYNOPTS  = -y $(PRDEPTH)/hw/chip/rcp/cs/syn			\
	   -y $(PRDEPTH)/hw/chip/lib/verilog/stdcell		\
	   -y $(PRDEPTH)/hw/chip/lib/verilog/ram		\
	    +libext+.v+.vsyn					\
	    -Mdir=syncsrc

#DUMP     = +dump

#
#  Default Targets

RTESTS  = rtest000 rtest001 rtest002 rtest003 rtest004 \
	  rtest005 rtest006 rtest007 rtest008

STESTS  = stest000 stest001 stest002 stest003 stest004 \
	  stest005 stest006 stest007 stest008

QTESTS  = qtest000 qtest001 qtest002 qtest003 qtest004 \
	  qtest005 qtest006 qtest007 qtest008

LDIRT  	= rsimv rsimv.daidir driver.v csrc				\
	  verilog.dump vcs.key vcs.log					\
	  cs_test cs_test_0.c bits_gram.y bits_scan.l bits_scan.c	\
	  $(INDATA)/inp??? $(INDATA)/inp???.tab				\
	  $(OUTDATA)/test???.mem $(OUTDATA)/test???.out			\
	  $(OUTDATA)/test???.tab fast???.out fast???.merge		\
	  qsim/*.tab qsim/*.sim* qsim/*.trc* qsim/*.simlog*

default rtests: $(RTESTS)

stests: $(STESTS)

qtests:	$(_FORCE)
	(cd qsim; make)

$(COMMONTARGS): $(COMMONPREF)$$@
	$(SUBDIRS_MAKERULE)

#
#  SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules

#
#  Use HOST compile
#
.c.o:
	$(HOST_CC) $(CFLAGS) -c $*.c

#
#  Target for creating all .1 files, Viewlogic netlists
#
$(WIR)/cs_test.1: $(_FORCE)
	cd $(WIR); $(MAKE)

#
#  Target for creating links
#
links:
	- ln -s $(SRC)/bits_gram.y . > /dev/null
	- ln -s $(SRC)/bits_scan.l . > /dev/null

#
#  Compile 'C' processes
#
bits_gram.y:	bits_scan.c

cs_test_0.c: $(WIR)/cs_test.1 cs_test.config $(XNET)
	$(XNET) -d $(WIR) cs_test -c cs_test.config

cs_test: links cs_test_0.c $(SIMLIB) $(TEST_OBJS)
	$(HOST_CC) $(CFLAGS) $(TEST_OBJS) $(LDFLAGS) -o $@


#
# Compile Verilog processes
#

driver.v: $(OUTDATA)/test000.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 $(OUTDATA)/test000.tab > $@

rsimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) -o $@ top_level.v driver.v

ssimv: top_level.vsyn driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ top_level.vsyn driver.v

#
#  Test Targets
#

# test000  reset tests
#

rtest000: rsimv $(OUTDATA)/test000.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest000: ssimv $(OUTDATA)/test000.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast000: $(OUTDATA)/test000.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test000.tab $*.out > $*.merge

$(OUTDATA)/test000.tab: cs_test $(INDATA)/inp000.tab $(OUTDATA)/test000.tab.base
	./cs_test -i 0 -o all -t 000
	cmp -s $@ $@.base

#
# test001  fifo tests
#
rtest001: rsimv $(OUTDATA)/test001.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest001: ssimv $(OUTDATA)/test001.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast001: $(OUTDATA)/test001.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test001.tab $*.out > $*.merge

$(OUTDATA)/test001.tab: cs_test $(INDATA)/inp001.tab $(OUTDATA)/test001.tab.base
	./cs_test -i 1 -o all -t 001
	cmp -s $@ $@.base

#
# test002  Command shuffle tests
#
rtest002: rsimv $(OUTDATA)/test002.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest002: ssimv $(OUTDATA)/test002.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast002: $(OUTDATA)/test002.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test002.tab $*.out > $*.merge

$(OUTDATA)/test002.tab: cs_test $(INDATA)/inp002.tab $(OUTDATA)/test002.tab.base
	./cs_test -i 2 -o all -t 002
	cmp -s $@ $@.base

#
# test003  More command shuffle tests
#
rtest003: rsimv $(OUTDATA)/test003.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest003: ssimv $(OUTDATA)/test003.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast003: $(OUTDATA)/test003.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test003.tab $*.out > $*.merge

$(OUTDATA)/test003.tab: cs_test $(INDATA)/inp003.tab $(OUTDATA)/test003.tab.base
	./cs_test -i 3 -o all -t 003
	cmp -s $@ $@.base

#
# test004  *sync command tests
#
rtest004: rsimv $(OUTDATA)/test004.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest004: ssimv $(OUTDATA)/test004.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast004: $(OUTDATA)/test004.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test004.tab $*.out > $*.merge

$(OUTDATA)/test004.tab: cs_test $(INDATA)/inp004.tab $(OUTDATA)/test004.tab.base
	./cs_test -i 4 -o all -t 004
	cmp -s $@ $@.base

#
# test005  ew_cs_busy tests
#
rtest005: rsimv $(OUTDATA)/test005.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest005: ssimv $(OUTDATA)/test005.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast005: $(OUTDATA)/test005.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test005.tab $*.out > $*.merge

$(OUTDATA)/test005.tab: cs_test $(INDATA)/inp005.tab $(OUTDATA)/test005.tab.base
	./cs_test -i 5 -o all -t 005
	cmp -s $@ $@.base

#
# test006 ms_busy tests
#
rtest006: rsimv $(OUTDATA)/test006.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest006: ssimv $(OUTDATA)/test006.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast006: $(OUTDATA)/test006.mem
	rsimv +mem=$? +dump | tee $*.out
	$(MERRG) $(OUTDATA)/test006.tab $*.out > $*.merge

$(OUTDATA)/test006.tab: cs_test $(INDATA)/inp006.tab $(OUTDATA)/test006.tab.base
	./cs_test -i 6 -o all -t 006
	cmp -s $@ $@.base

#
# texel_size tests
#
rtest007: rsimv $(OUTDATA)/test007.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest007: ssimv $(OUTDATA)/test007.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast007: $(OUTDATA)/test007.mem
	rsimv +mem=$? | tee $*.out
	$(MERRG) $(OUTDATA)/test007.tab $*.out > $*.merge

$(OUTDATA)/test007.tab: cs_test $(INDATA)/inp007.tab $(OUTDATA)/test007.tab.base
	./cs_test -i 7 -o all -t 007
	cmp -s $@ $@.base

#
# copy_fill tests
#
rtest008: rsimv $(OUTDATA)/test008.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest008: ssimv $(OUTDATA)/test008.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

fast008: $(OUTDATA)/test008.mem
	rsimv +mem=$? | tee $*.out
	$(MERRG) $(OUTDATA)/test008.tab $*.out > $*.merge

$(OUTDATA)/test008.tab: cs_test $(INDATA)/inp008.tab $(OUTDATA)/test008.tab.base
	./cs_test -i 8 -o all -t 008
	cmp -s $@ $@.base