top_level.vsyn
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Revision: 1.1.1.1 $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: top_level
// description: Top Level Driver
//
// designer: Rob Moore
// date: 8/23/94
//
// updated: 9/22/94 (tonyd)
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
module top_level();
wire [2:0] tile_addr;
wire [47:0] cs_tc_data;
wire we_tile_size, we_tile_attr;
wire [63:0] cs_ew_data;
wire cs_ew_newprim;
wire cs_xbus_req;
wire [5:0] cmd;
wire start_prim, attr_valid, cmd_busy;
wire [63:0] xbus_cs_data;
wire xbus_cs_valid;
wire ew_cs_busy;
wire ms_busy;
wire rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load;
wire [1:0] texel_size;
wire reset_l, clk;
// instance cs unit
cs cs (.tile_addr(tile_addr), .cs_tc_data(cs_tc_data),
.we_tile_size(we_tile_size), .we_tile_attr(we_tile_attr),
.cs_ew_data(cs_ew_data), .cs_ew_newprim(cs_ew_newprim),
.cs_xbus_req(cs_xbus_req), .cmd(cmd), .start_prim(start_prim),
.attr_valid(attr_valid), .cmd_busy(cmd_busy),
.xbus_cs_data(xbus_cs_data), .xbus_cs_valid(xbus_cs_valid),
.ew_cs_busy(ew_cs_busy), .ms_busy(ms_busy),
.rel_sync_tile(rel_sync_tile), .rel_sync_pipe(rel_sync_pipe),
.rel_sync_full(rel_sync_full), .rel_sync_load(rel_sync_load),
.texel_size(texel_size), .copy_fill(copy_fill),
.reset_l(reset_l), .gclk(clk), .clk(clk));
// instance driver
driver driver(.xbus_cs_data(xbus_cs_data), .xbus_cs_valid(xbus_cs_valid),
.ew_cs_busy(ew_cs_busy), .ms_busy(ms_busy),
.rel_sync_tile(rel_sync_tile), .rel_sync_pipe(rel_sync_pipe),
.rel_sync_full(rel_sync_full), .rel_sync_load(rel_sync_load),
.texel_size(texel_size), .copy_fill(copy_fill), .reset_l(reset_l),
.w_addr_in({cs.clklogic.\w_addr_in[5] , cs.clklogic.wr_adrs}),
.read_adrs(cs.gclklogic.read_adrs),
.shf_state({cs.gclklogic.\shf_state[4] , cs.gclklogic.\shf_state[3] ,
cs.gclklogic.\shf_state[2] , cs.gclklogic.\shf_state[1] ,
cs.gclklogic.\shf_state[0] }),
.sync_tile_state(cs.gclklogic.decode.sync_tile_state),
.sync_pipe_state(cs.gclklogic.decode.sync_pipe_state),
.sync_full_state(cs.gclklogic.decode.sync_full_state),
.sync_load_state(cs.gclklogic.decode.sync_load_state_reg.q),
.tile_addr(tile_addr), .cs_tc_data(cs_tc_data),
.we_tile_size(we_tile_size), .we_tile_attr(we_tile_attr),
.cs_ew_data(cs_ew_data), .cs_ew_newprim(cs_ew_newprim),
.cs_xbus_req(cs_xbus_req), .cmd(cmd),
.start_prim(start_prim), .attr_valid(attr_valid), .cmd_busy(cmd_busy),
.clk(clk));
// kill simulation when tabular file read
always @(driver.EndVectors)
$finish;
// dump file
initial
begin
if ($test$plusargs("dump"))
$dumpvars;
end
endmodule // top_level