top_level.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: top_level
// description: Top Level Driver for RDP Verilog Simulation
//
// designer: Rob Moore
// date: 9/16/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
`define CYCLE_TIME 1600
module top_level();
// Connected inputs
wire cs_xbus_req;
wire [63:0] xbus_cs_data;
wire xbus_cs_valid;
wire reset;
wire gclk;
// unconnected inputs
reg load_dv; // valid load data on copy_load bus
reg [7:0] mem_r; // from mem_span unit
reg [7:0] mem_g;
reg [7:0] mem_b;
reg [2:0] mem_a;
reg [17:0] mem_z; // z and delta from memory (fp format)
reg rel_sync_full;
reg flush;
reg [1:256*8] tmem; // filename for Tmem contents
reg [63:0] mem_word; // word for loading Tmem
reg [8:0] i; // index into Tmem
integer tfp; // file pointer for Tmem file
// instance driver
driver driver(.request(cs_xbus_req),
.xbus_data(xbus_cs_data),
.xbus_valid(xbus_cs_valid),
.reset(reset),
.gclk(gclk));
// instance RDP minus memspan for now
rdp_ms rdp( .cs_xbus_req(cs_xbus_req),
.xbus_cs_data(xbus_cs_data),
.xbus_cs_valid(xbus_cs_valid),
.reset_l(reset),
.gclk(gclk), .clk(gclk),
.load_dv(load_dv),
.flush(flush),
.mem_r(mem_r),
.mem_g(mem_g),
.mem_b(mem_b),
.mem_a(mem_a),
.mem_z(mem_z),
.rel_sync_full(rel_sync_full));
// Instance Display
display display ( .gclk(gclk),
.span_r(rdp.span_r),
.span_g(rdp.span_g),
.span_b(rdp.span_b),
.span_a(rdp.span_a),
.span_clr_we(rdp.bl.span_color_we),
.st_span(rdp.ew.ew_cv_newspan),
.start_x(rdp.ew.ew_cv_start_x),
.new_prim(rdp.cs.cs_ew_newprim),
.y_h(rdp.cs.cs_ew_data));
// Init unconnected inputs with zero
initial
begin
load_dv = 0;
flush = 0;
mem_r[7:0] = 8'h0;
mem_g[7:0] = 8'h0;
mem_b[7:0] = 8'h0;
mem_a[2:0] = 3'h0;
mem_z[17:0] = 18'h0;
rel_sync_full = 0;
end
// Load Tmem
initial
begin
if ($getstr$plusarg("tmem=", tmem) == 1)
begin
tfp = $open_mem_file(tmem);
if (tfp == 0)
$write("Cannot open Tmem file\n");
else
begin
for(i = 0; i < 256; i = i + 1) // low Tmem addresses
begin
if(($read_mem_file(tfp, mem_word)) != -1)
begin
rdp.tm.low_half.bnk0.ram_primh[i] = mem_word[63:56];
rdp.tm.low_half.bnk0.ram_priml[i] = mem_word[55:48];
rdp.tm.low_half.bnk1.ram_primh[i] = mem_word[47:40];
rdp.tm.low_half.bnk1.ram_priml[i] = mem_word[39:32];
rdp.tm.low_half.bnk2.ram_primh[i] = mem_word[31:24];
rdp.tm.low_half.bnk2.ram_priml[i] = mem_word[23:16];
rdp.tm.low_half.bnk3.ram_primh[i] = mem_word[15:8];
rdp.tm.low_half.bnk3.ram_priml[i] = mem_word[7:0];
end
end
for(i = 0; i < 256; i = i + 1) // high Tmem addresses
begin
if(($read_mem_file(tfp, mem_word)) != -1)
begin
rdp.tm.hi_half.bnk0.ram_primh[i] = mem_word[63:56];
rdp.tm.hi_half.bnk0.ram_priml[i] = mem_word[55:48];
rdp.tm.hi_half.bnk1.ram_primh[i] = mem_word[47:40];
rdp.tm.hi_half.bnk1.ram_priml[i] = mem_word[39:32];
rdp.tm.hi_half.bnk2.ram_primh[i] = mem_word[31:24];
rdp.tm.hi_half.bnk2.ram_priml[i] = mem_word[23:16];
rdp.tm.hi_half.bnk3.ram_primh[i] = mem_word[15:8];
rdp.tm.hi_half.bnk3.ram_priml[i] = mem_word[7:0];
end
end
end
end
end
// dump file
initial
begin
if($test$plusargs("dump"))
$dumpvars;
end
endmodule // top_level