/************************************************************************
  Variations on the Nair, Thatte, Abraham (NTA) test by Nair, Thatte, and
  Abraham for stuck-at and coupling faults.

  ----------------------------------------------------------------------

  While a complete NTA calls for each bit of the memory under test to be
  treated as a cell, this test (Project Reality's own flavor)
  incorporates several variations that use various groupings of bits to
  reduce the test duration and yet provide a high confidence level.

  We begin by assuming that the memory module (DMEM) is comprised of
  address decoder, pre-charged bit-lines, bit cells, sense-amplifiers,
  and output buffers/registers.  The address decoder can be either
  wired-OR or wired-AND types.  Bit-lines are arranged in the same order
  as the bits appear in a 32-bit data word.  Our key assumptions that
  allows us to reduce the length of Test B is: coupling faults occur
  mainly between bits in different words (often along a bit-line), or
  between adjacent bits in the same word.

  Each variation uses the same 8-step algorithm:

    0)	for (i=1; i<=N; i++) { Wi=0;               }

    1)	for (i=1;   i<=N;   i++) { Ri(=0); Wi=1;       }
	for (i=N-1; i>=1;   i--) { Ri(=1);             }

    2)	for (i=1;   i<=N;   i++) { Ri(=1); Wi=0;       }
	for (i=N-1; i>=1;   i--) { Ri(=0);             }

    3)	for (i=N;   i<=1;   i--) { Ri(=0); Wi=1;       }
	for (i=1;   i>=N-1; i++) { Ri(=1);             }

    4)	for (i=N;   i<=1;   i--) { Ri(=1); Wi=0;       }
	for (i=1;   i>=N-1; i++) { Ri(=0);             }

    5)	for (i=1;   i<=N;   i++) { Ri(=0); Wi=1; Wi=0; }
	for (i=N-1; i>=1;   i--) { Ri(=0);             }

    6)	for (i=N;   i<=1;   i--) { Ri(=0); Wi=1; Wi=0; }
	for (i=1;   i>=N-1; i++) { Ri(=0);             }

    S)  for (i=1;   i<=N;   i++) { Wi=1;               }

    7)	for (i=1;   i<=N;   i++) { Ri(=1); Wi=0; Wi=1; }
	for (i=N-1; i>=1;   i--) { Ri(=1);             }

    8)	for (i=N;   i<=1;   i--) { Ri(=1); Wi=0; Wi=1; }
	for (i=1;   i>=N-1; i++) { Ri(=1);             }

 ************************************************************************/
#define FEED	0xFEED
#define ZERO	$0	/* zero register			*/
#define TID	$1	/* test ID				*/
#define SID	$2	/* step ID				*/
#define TREG	$3	/* test (scratch) register		*/
#define INCR	$4	/* address increment register (4, -4)	*/
#define MEND	$5	/* memory "end" (constant) register	*/
#define CHKV	$7	/* set value register			*/
#define RET2	$26	/* return register for nested calls	*/
#define ADDR	$27	/* address register (also loop start)	*/
#define PAT1	$28	/* pattern 1 register			*/
#define PAT2	$29	/* pattern 2 register			*/
#define STOP	$30	/* loop stop register			*/
#define RETN	$31	/* procedure call return register	*/

	.base 0x04001000

	ori	MEND, ZERO, 0x0FFC
	or	CHKV, ZERO, ZERO
	addi	CHKV, CHKV, 1
	
	or	PAT1, ZERO, ZERO
	nor	PAT2, ZERO, ZERO
	jal	Test
	ori	TID,  ZERO, 1
	addi	CHKV, CHKV, 2

	or	PAT1, ZERO, ZERO
	lui	PAT2, 0x5555
	ori	PAT2, PAT2, 0x5555
	jal	Test
	ori	TID,  ZERO, 2
	addi	CHKV, CHKV, 4

	nor	PAT1, ZERO, ZERO
	lui	PAT2, 0x5555
	ori	PAT2, PAT2, 0x5555
	jal	Test
	ori	TID,  ZERO, 3
	addi	CHKV, CHKV, 8

	or	PAT1, ZERO, ZERO
	lui	PAT2, 0xAAAA
	ori	PAT2, PAT2, 0xAAAA
	jal	Test
	ori	TID,  ZERO, 4
	addi	CHKV, CHKV, 16

	nor	PAT1, ZERO, ZERO
	lui	PAT2, 0xAAAA
	ori	PAT2, PAT2, 0xAAAA
	jal	Test
	ori	TID,  ZERO, 5
	addi	CHKV, CHKV, 32

	lui	PAT1, 0x5555
	ori	PAT1, PAT1, 0x5555
	lui	PAT2, 0xAAAA
	ori	PAT2, PAT2, 0xAAAA
	jal	Test
	ori	TID,  ZERO, 6
	addi	CHKV, CHKV, 64

	j	End

Test:	or	RET2, RETN, ZERO

	/* Step Reset */
	or	ADDR, ZERO, ZERO
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	Reset
	ori	SID,  ZERO, 0x000a

	/* Step 1 */
	or	ADDR, ZERO, ZERO
	jal	RdT1
	ori	SID,  ZERO, 0x001a
	addi	ADDR, MEND, -4
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	xor	PAT1, PAT1, PAT2
	xor	PAT2, PAT1, PAT2
	xor	PAT1, PAT1, PAT2
	jal	Read
	ori	SID,  ZERO, 0x001b

	/* Step 2 */
	or	ADDR, ZERO, ZERO
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	RdT1
	ori	SID,  ZERO, 0x002a
	addi	ADDR, MEND, -4
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	xor	PAT1, PAT1, PAT2
	xor	PAT2, PAT1, PAT2
	xor	PAT1, PAT1, PAT2
	jal	Read
	ori	SID,  ZERO, 0x002b

	/* Step 3 */
	or	ADDR, MEND, MEND
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	RdT1
	ori	SID,  ZERO, 0x003a
	addi	ADDR, ZERO, 4
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	xor	PAT1, PAT1, PAT2
	xor	PAT2, PAT1, PAT2
	xor	PAT1, PAT1, PAT2
	jal	Read
	ori	SID,  ZERO, 0x003b

	/* Step 4 */
	or	ADDR, MEND, MEND
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	RdT1
	ori	SID,  ZERO, 0x004a
	addi	ADDR, ZERO, 4
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	xor	PAT1, PAT1, PAT2
	xor	PAT2, PAT1, PAT2
	xor	PAT1, PAT1, PAT2
	jal	Read
	ori	SID,  ZERO, 0x004b

	/* Step 5 */
	or	ADDR, ZERO, ZERO
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	RdT2
	ori	SID,  ZERO, 0x005a
	addi	ADDR, MEND, -4
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	Read
	ori	SID,  ZERO, 0x005b
	
	/* Step 6 */
	or	ADDR, MEND, MEND
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	RdT2
	ori	SID,  ZERO, 0x006a
	addi	ADDR, ZERO, 4
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	Read
	ori	SID,  ZERO, 0x006b

	/* Step Set */
	xor	PAT1, PAT1, PAT2
	xor	PAT2, PAT1, PAT2
	xor	PAT1, PAT1, PAT2
	or	ADDR, ZERO, ZERO
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	Reset
	ori	SID,  ZERO, 0x006c

	/* Step 7 */
	or	ADDR, ZERO, ZERO
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	RdT2
	ori	SID,  ZERO, 0x007a
	addi	ADDR, MEND, -4
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	Read
	ori	SID,  ZERO, 0x007b

	/* Step 8 */
	or	ADDR, MEND, MEND
	or	STOP, ZERO, ZERO
	addi	INCR, ZERO, -4
	jal	RdT2
	ori	SID,  ZERO, 0x008a
	addi	ADDR, ZERO, 4
	or	STOP, MEND, MEND
	addi	INCR, ZERO, 4
	jal	Read
	ori	SID,  ZERO, 0x008b

	/* Return */
	jr	RET2
	nop

	/********************************
	  Read( TREG, ADDR, PAT1, STOP,
		INCR, RETN)
	 ********************************/
Read:	lw	TREG, 0 (ADDR)
	bne	TREG, PAT1, Fail
	nop
	bne	ADDR, STOP, Read
	add	ADDR, ADDR, INCR
	jr	RETN
	nop

	/****************************************
	  RdT1( TREG, ADDR, PAT1, PAT2, STOP,
		INCR, RETN)
	 ****************************************/
RdT1:	lw	TREG, 0 (ADDR)
	bne	TREG, PAT1, Fail
	sw	PAT2, 0 (ADDR)
	bne	ADDR, STOP, RdT1
	add	ADDR, ADDR, INCR
	jr	RETN
	nop

	/****************************************
	  RdT2( TREG, ADDR, PAT1, PAT2, STOP,
		INCR, RETN)
	 ****************************************/
RdT2:	lw	TREG, 0 (ADDR)
	bne	TREG, PAT1, Fail
	sw	PAT2, 0 (ADDR)
	sw	PAT1, 0 (ADDR)
	bne	ADDR, STOP, RdT2
	add	ADDR, ADDR, INCR
	jr	RETN
	nop

	/****************************************
	  Reset( PAT1, ADDR, STOP, INCR, RETN)
	 ****************************************/
Reset:	sw	PAT1, 0 (ADDR)
	bne	ADDR, STOP, Reset
	add	ADDR, ADDR, INCR
	jr	RETN
	nop

End:	ori	TREG, ZERO, 0x007F
	bne	TREG, CHKV, Fail
	nop
	or	SID,  ZERO, ZERO
	ori	TID,  ZERO, FEED
Fail:	break