ls_ex_rot_values.v
1.68 KB
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module ls_ex_rot_values(rd_addr_30,
rd_inst_data_30,
rd_elem_num,
clk,
//
ex_rot_addr_low,
ex_rot_data0,
ex_rot_data1,
ex_rot_data2,
ex_rot_data3,
ex_rot_data4,
ex_rot_data5,
ex_rot_data6,
ex_rot_data9
);
input [3:0] rd_addr_30,rd_inst_data_30,rd_elem_num;
input clk;
output [3:0] ex_rot_addr_low;
output [3:0] ex_rot_data0;
output [3:0] ex_rot_data1;
output [3:0] ex_rot_data2;
output [3:0] ex_rot_data3;
output [3:0] ex_rot_data4;
output [3:0] ex_rot_data5;
output [3:0] ex_rot_data6;
output [3:0] ex_rot_data9;
reg [3:0] ex_inst_data_30,ex_addr_30,elem_num;
reg [3:0] num0,num1,num2,num3,num4;
wire [3:0] num0_x = rd_inst_data_30 - {!rd_elem_num[3], rd_elem_num[2:0]};
wire [3:0] num1_x = rd_inst_data_30 - rd_elem_num - 4'h1;
wire [3:0] num2_x = rd_inst_data_30 - rd_elem_num;
wire [3:0] num3_x = rd_inst_data_30 - 4'h3;
wire [3:0] num4_x = rd_inst_data_30 - 4'h2;
always @(posedge clk) ex_addr_30 <= rd_addr_30;
always @(posedge clk) ex_inst_data_30 <= rd_inst_data_30;
always @(posedge clk) elem_num <= rd_elem_num;
always @(posedge clk) num0 <= num0_x;
always @(posedge clk) num1 <= num1_x;
always @(posedge clk) num2 <= num2_x;
always @(posedge clk) num3 <= num3_x;
always @(posedge clk) num4 <= num4_x;
assign ex_rot_addr_low = ex_addr_30 + ex_inst_data_30;
assign ex_rot_data0 = ex_addr_30 + num0;
assign ex_rot_data1 = ex_addr_30 + num1;
assign ex_rot_data2 = ex_addr_30 + num2;
assign ex_rot_data3 = ex_addr_30 + num3;
assign ex_rot_data4 = ex_addr_30 + num4;
assign ex_rot_data5 = elem_num - 4'h2;
assign ex_rot_data6 = -elem_num;
assign ex_rot_data9 = -elem_num + 4'h2;
endmodule